Altera Interlaken MegaCore Function Manuel d'utilisateur Page 45
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 4: Functional Description 4–19
Receive Path
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
Channel Filtering Blocks
Each channel filtering block identifies the data that targets the channel with which it is
associated. It identifies the target channel of a burst from the burst control words. The
channel filtering block passes that data through to a regrouper, filtering out the data
that targets the other channel. As the channel filter filters the data, it rearranges each
data sample so that the valid data and idle bytes for its associated channel are the
most significant bytes.
The following example illustrates the function of the channel filtering blocks in a
variation with a 256-bit channel width. Table 4–6 shows example four-word-wide raw
data output from the RX MAC block. Each table cell represents a 64-bit word.
Table 4–7 shows the resulting output stream from the RX channel 0 filter and
Table 4–8 shows the resulting output stream from the RX channel 1 filter.
Packet Regrouper
The packet regrouper for each channel receives the filtered data and rearranges each
channel data sample so that the valid bytes are the most significant bytes, removing
all control words. The information is instead conveyed by using the
rx_chX_dataout_empty
vector to indicate the number of invalid bytes on the
rx_chX_dataout_data
bus in the current
rx_mac_c_clk
clock cycle. Any
start-of-packet and end-of-packet information is likewise conveyed in separate
signals,
rx_chX_dataout_startofpacket
and
rx_chX_dataout_endofpacket
, which
are asserted during the clock cycle in which the appropriate condition holds.
The packet regrouper signals the application channel that it has data ready for
transmission on the channel, by asserting the
rx_chX_dataout_valid
signal after it
loads the data on the
rx_chX_dataout_data
bus. Refer to Table 4–5 on page 4–12 for
the channel data bus width.
Table 4–6. Example Raw Data Output From RX MAC Block
t = 0 BC SOP ch0 Data 0 Data 1 Data 2
t = 1 Data 3 Data 4 BC EOP ch0, SOP ch1 Data 5
t = 2 Data 6 Data 7 Data 8 Data 9
t = 3 Data 10 Data 11 IDLE EOP ch1 —
Table 4–7. Output Stream From RX Channel 0 Filter
t’= 0 BC SOP ch0 Data 0 Data 1 Data 2
t’ = 1 Data 3 Data 4 BC EOP ch0 —
t’ = 2 — — — —
t’ = 3 — — — —
Table 4–8. Output Stream From RX Channel 1 Filter
t" = 0————
t" = 1 BC SOP ch1 Data 5 — —
t" = 2 Data 6 Data 7 Data 8 Data 9
t" = 3 Data 10 Data 11 IDLE EOP ch1 —
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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