Altera Interlaken MegaCore Function Manuel d'utilisateur Page 54
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
5–2 Chapter 5: Signals
Interlaken Interface and External Transceiver Interface Signals
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
Interlaken Interface Data and Clock Signals
Table 5–1 lists the Interlaken interface data and clock signals when you turn off
Exclude transceivers.
Table 5–1. Interlaken Data Interface Signals (Part 1 of 2)
Signal Direction Description
rx_serial_dataN_export
[M:0]
Input
Differential high-speed serial input data to the transceiver. It is connected to the
corresponding transmit data lines of the Interlaken link partner.
N corresponds to the HSIO bank number. N = 0 for 4-lane variations; N = {0,1} for
8- and 10-lane variations, N = {0,1,2} for 12-lane variations, and N = {0,1,2,3} for
20-lane variations. The width of the port is 4 (M=3) for 4-, 8-, and 12-lane
variations, and 5 (M=4) for 10- and 20-lane variations.
Lane 0 holds the MSB of the input data, which is input to the HSIO bank with the
highest number. Refer to Figure 4–2 on page 4–6 through Figure 4–6 on
page 4–9.
In an 8-lane variation,
rx_serial_data1_export[3]
connects to lane 0,
rx_serial_data1_export[2]
connects to lane 1, and so on;
rx_serial_data0_export[2]
connects to lane 5,
rx_serial_data0_export[1]
connects to lane 6, and
rx_serial_data0_export[0]
connects to lane 7.
In a 20-lane variation,
rx_serial_data3_export[4]
connects to lane 0,
rx_serial_data3_export[3]
connects to lane 1, and so on;
rx_serial_data2_export[4]
connects to lane 5,
rx_serial_data2_export[3]
connects to lane 6, and so on;
rx_serial_data1_export[4]
connects to lane 10;
rx_serial_data1_export[0]
connects to lane 14;
rx_serial_data0_export[4]
connects to lane 15, and
rx_serial_data0_export[0]
connects to lane 19.
tx_serial_dataN_export
[M:0]
Input
Differential high-speed serial output data from the transceiver. It is connected to
the corresponding receive data lines of the Interlaken link partner.
N corresponds to the HSIO bank number. N = 0 for 4-lane variations; N = {0,1} for
8- and 10-lane variations, N = {0,1,2} for 12-lane variations, and N = {0,1,2,3} for
20-lane variations. The width of the port is 4 (M=3) for 4-, 8-, and 12-lane
variations, and 5 (M=4) for 10- and 20-lane variations.
Lane 0 holds the MSB of the output data, which is output on the HSIO bank with
the highest number. Refer to Figure 4–2 on page 4–6 through Figure 4–6 on
page 4–9.
In an 8-lane variation, lane 0 is output on
tx_serial_data1_export[3]
,
lane 1 is output on
tx_serial_data1_export[2]
, and so on;
lane 5 is output on
tx_serial_data0_export[2]
,
lane 6 is output on
tx_serial_data0_export[1]
, and
lane 7 is output on
tx_serial_data0_export[0]
.
In a 20-lane variation, lane 0 is output on
tx_serial_data3_export[4]
,
lane 1 is output on
tx_serial_data3_export[3]
, and so on;
lane 5 is output on
tx_serial_data2_export[4]
,
lane 6 is output on
tx_serial_data2_export[3]
, and so on;
lane 10 is output on
tx_serial_data1_export[4]
;
lane 14 is output on
tx_serial_data1_export[0]
;
lane 15 is output on
tx_serial_data0_export[4]
, and
lane 19 is output on
tx_serial_data0_export[0]
.
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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