Altera Integer Arithmetic IP Manuel d'utilisateur Page 54
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ALTERA_MULT_ADD (Multiply-Adder)
6
2014.12.19
UG-01063
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The ALTERA_MULT_ADD megafunction allows you to implement a multiplier-adder.
The following figure shows the ports for the ALTERA_MULT_ADD megafunction.
Figure 6-1: ALTERA_MULT_ADD Ports
dataa[]
inst
ALTERA_MULT_ADD
datab[]
signa
scanouta[]
signb
result[]
datac[]
coefsel1[]
addnsub1
addnsub3
clock0
ena0
accum_sload
chainin[]
coefsel2[]
coefsel3[]
coefsel0[]
aclr[]
scanina[]
sload_accum
clock1
clock2
ena1
ena2
aclr0
aclr1
A multiplier-adder accepts pairs of inputs, multiplies the values together and then adds to or subtracts
from the products of all other pairs.
The ALTERA_MULT_ADD megafunction also offers many variations in dedicated DSP block circuitry.
Data input sizes of up to 18 bits are accepted. Because the DSP blocks allow for one or two levels of 2-
input add or subtract operations on the product, this function creates up to four multipliers.
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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