
Altera Corporation A–25
HardCopy II Clock Uncertainty Calculator User Guide
Figure A–26 shows an example of a clock-pair = CLK5 to CLK9
Figure A–26. Inter-Clock Domain with Two Independent Clocks and Cascaded PLLs on the Source Clock
Table A–26 shows input of the PLL index for Figure A–26, with respect to
the source and destination clocks.
PLL12
PLL2
INBUF10
Clock
Source
Register
Destinatio
Register
CLK3
CLK5
INBUF11
Destination
CLK9
Table A–26. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
12 2 0 —
Commentaires sur ces manuels