Altera HardCopy II Clock Uncertainty Calculator Manuel d'utilisateur Page 44

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A–12 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide
I/O Interface without PLL
Figure A–12 shows an example of a clock-pair = CLK2 to Off-chip
Figure A–12. Output Interface with a PLL
Table A–12 shows input of the PLL index for Figure A–12, with respect to
the source and destination clocks.
I/O Interface
without PLL
This section provides clock transfer examples for an I/O interface
without a PLL.
INBUF
CLK2
Source
Register
PLL7
DAT
A
Source
Clock
Table A–12. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
7—0
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