Altera FIR Compiler II MegaCore Function Manuel d'utilisateur Page 54
- Page / 57
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Figure 4-28: Timing Diagram of a Single-Channel Filter with 4 Coefficient Banks
clk
ast_sink_valid
ast_sink_data[9:0]
bankin_0[1:0]
xin_0[7:0]
xout_v[0]
xout_0[21:0]
256 -478 -179 118 408 -259 -159 135 427 -433 -79 122 481 -396 -15 48 429 -262
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2
34 77 118 -104 -3 97 -121 -85 79 -79 122 -31 116 -15 48 -83 -6
411 279
0
0
0
0
0
1
Figure 4-29: Timing Diagram of a Four-Channel Filter with 4 Coefficient BanksEach channel has a
separate corresponding coefficient set. The bank inputs for different channels are driven with their
channel number respectively throughout the filter operation
clk
ast_sink_valid
ast_sink_data[39:0]
bankin_0[1:0]
xin_0[7:0]
bankin_1[1:0]
xin_1[7:0]
bankin_2[1:0]
xin_2[7:0]
bankin_3[1:0]
xin_3[7:0]
xout_v[0]
xout_0[21:0]
xout_1[21:0]
xout_2[21:0]
xout_3[21:0]
-15... -17... -55... -20...
-23...
-30...
-30...
-16...
-21...
-24...
-14...
-14...
-12...
-41...
-25...
-17...
-26...
-25... -20... -80... -13...
-41 24 29 -65 -109 34 -15 18 77 -82 25 127 -42 -18 -96 -4 79 27 88 -91 -84
52 67 71 -78 -82 -22 55 115 120 -51 -28 -124 -81 -16 67 -104 47 -27 50 33
46 -37 22 29 -102 -125 -12 -10 -21 -48 56 15 32 31 -23 125 -105 57 -17 12 93
109 96 -52 67 33 -29 99 57 29 125 122 -114 -39 21 88 4 22 61 -8 -126
-82 -75 7 -12 -261 -162 16 231 550
1....
104 186 157 -412 -804 -464 1040 2...
46 -83 -33 219 -148 -402 5...
109 -13 -148 337 -278 -441 8...
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
2
3
Related Information
Loading Coefficients from a File on page 3-3
FIR II IP Core Coefficient Reloading
You access the internal data coefficients via a memory-mapped interface that consists of the input
address, write data, write enable, read data, and read valid signals. The Avalon Memory-Mapped (Avalon-
MM) interfaces operate as read and write interfaces on the master and slave components in a memory-
mapped system. The memory-mapped system components include microprocessors, memories, UARTs,
timers, and a system interconnect fabric that connects the master and slave interfaces. The Avalon-MM
interfaces describe a wide variety of components, from an SRAM that supports simple, fixed-cycle read
and write transfers to a complex, pipelined interface capable of burst transfers. In Read mode, the IP core
reads the memory-mapped coefficients over a specified address range. In Write mode, the IP core writes
the coefficients over a specified address range. In Read/Write mode, you can read or write the coefficients
over a specified address range. You can use a separate bus clock for this interface. When you do not
enable coefficient reloading option, the processor cannot access the specified address range, and the IP
core does not read or write the coefficient data.
Coefficient reloading starts anytime during the filter run time. However, you must reload the coefficients
only after you obtain all the desired output data to avoid unpredictable results. If you use multiple
coefficient banks, you can reload coefficient banks that are not used and switch over to the new coefficient
set when coefficient reloading is complete. You must toggle the coeff_in_areset signal before reloading
UG-01072
2014.12.15
FIR II IP Core Coefficient Reloading
4-21
FIR II IP Core Functional Description
Altera Corporation
Send Feedback
- FIR II IP Core 1
- Contents 2
- FIR II IP Core User Guide 3
- FIR II IP Core Features 5
- Device Family Support 5
- DSP IP Core Verification 6
- About the FIR II IP Core 10
- Altera Corporation 10
- Send Feedback 10
- OpenCore Plus IP Evaluation 16
- Related Information 17
- Search for installed IP cores 18
- UG-01072 19
- 2014.12.15 19
- File Name Description 21
- Quartus II 24
- Design Flow 24
- Gate-Level Simulation 24
- RTL Simulation 24
- FIR II IP Core Parameters 26
- Parameter Value Description 27
- Coefficient Parameters 28
- Input and Output Options 29
- Signed Fractional Binary 30
- Using M-RAM Threshold 33
- Subscribe 34
- Avalon-ST Sink Interface 35
- Single Channel on Single Wire 36
- Avalon-ST Source Interface 39
- FIR II IP Core Signals 41
- Vectorized Inputs 45
- Channelization 46
- Eight Channels on Three Wires 48
- Four Channels on Four Wires 48
- Super Sample Rate 52
- Document Revision History 57
Produits connexes et manuels pour Instruments de mesure Altera FIR Compiler II MegaCore Function
Instruments de mesure Altera HardCopy II Clock Uncertainty Calculator Manuel d'utilisateur
(62 pages)
(62 pages)
Instruments de mesure Altera High-Speed Development Kit, Stratix GX Edition Manuel d'utilisateur
(140 pages)
(140 pages)
Instruments de mesure Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuel d'utilisateur
(196 pages)
(196 pages)
Instruments de mesure Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur
(413 pages)
(413 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.056 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels