Altera FIR Compiler II MegaCore Function Manuel d'utilisateur télécharger pdf (Page 12)

Parameters

ALM

DSP

Blocks

Memory Registers

MAX

(MHz)

Channel Wires Filter Type Coefficients M10K M20K Primary Secondary

1 super

sample

— Single rate Write 369 20 0 — 704 23 27

1 — Single rate Write 227 10 0 — 535 0 25

1 Half

Band

— Single rate — 187 5 0 — 273 44 28

1 Half

Band

— Single rate Write 274 5 0 — 506 19 27

1 — Single rate Multiple

banks

110 10 0 — 187 41 25

1 — Single rate Multiple

banks;

Write

375 10 0 — 349 32 25

Table 1-5: FIR II IP Core Performance—Stratix V Devices

Typical expected performance using the Quartus II software with Stratix V (5SGSMD4H2F35C2) devices.

Parameters

ALM

DSP

Blocks

Memory Registers

MAX

(MHz)

Channel Wires Filter Type Coefficients M10K M20K Primary Secondary

8 2 Decimation — 1,609 24 — 0 1,231 60 45

8 2 Decimation Write 2,319 24 — 0 2,077 66 45

8 2 Fractional

Rate

— 1,350 16 — 0 2,099 88 44

8 2 Fractional

Rate

Write 1,771 16 — 0 2,291 78 45

8 2 Fractional

Rate

— 1,457 16 — 0 2,213 88 44

8 2 Fractional

Rate

Write 1,873 16 — 0 2,418 89 45

8 2 Interpolation — 1,777 32 — 0 2,303 15 44

8 2 Interpolation Write 2,081 32 — 0 3,009 26 45

8 2 Interpolation Multiple

banks

1,825 32 — 0 2,473 39 43

UG-01072

2014.12.15

FIR II IP Core Performance and Resource Utilization

1-9

About the FIR II IP Core

Altera Corporation

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Altera FIR Compiler II MegaCore Function Manuel d'utilisateur Page 12

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