Altera Designing With Low-Level Primitives Manuel d'utilisateur télécharger pdf (Page 50)

2–28 Altera Corporation

Designing with Low-Level Primitives User Guide April 2007

Primitives

Example 2–19 shows a VHDL component declaration for an LCELL

primitive instantiation.

Example 2–19. LCELL Primitive Instantiation, VHDL Component Declaration

COMPONENT LCELL

PORT (a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

DFF

The registers in an Altera FPGA support an assortment of configurations,

and you have the option of instantiating the following configurations:

■ A DFFE (data flipflop with enable) primitive

■ A DFFEA (data flipflop with enable and asynchronous load)

primitive with additional ALOAD asynchronous load and ADATA

data signals

■ A DFFEAS (data flipflop with enable and both synchronous and

asynchronous load)

Example 2–20 shows a a Verilog HDL example of a DFF primitive

instantiation.

Example 2–20. DFF Primitive Instantiation, Verilog HDL

dffeas <instance_name> (.d(<input_wire>), .clk(<input_wire>),

.clrn(<input_wire>), .prn(<input_wire>), .ena(<input_wire>),

.asdata(<input_wire>), .aload(<input_wire>), .sclr(<input_wire>),

.sload(<input_wire>), .q(<output_wire>);

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Altera Designing With Low-Level Primitives Manuel d'utilisateur Page 50