Altera Designing With Low-Level Primitives Manuel d'utilisateur télécharger pdf (Page 30)

2–8 Altera Corporation

Designing with Low-Level Primitives User Guide April 2007

Primitives

ALT_IOBUF

The primitive allows you to make a location assignment,

io_standard assignment, current_strength assignment,

termination assignment, and allows you to determine whether or not to

use weak pull-up resistor, whether or not to enable bus-hold circuitry

and/or a slow_slew_rate assignment to a bidirectional pin from a

lower-level entity.

Table 2–4 lists the ports and parameters of the ALT_IOBUF primitive, and

their respective descriptions and possible values.

Example 2–7 shows a Verilog HDL example of an ALT_IOBUF primitive

instantiation.

Example 2–7. ALT_IOBUF Primitive Instantiation, Verilog HDL

alt_iobuf my_iobuf (.i(internal_sig1), .oe(enable_sig),

.o(internal_sig2), .io(bidir));

//bidir must be declared as an inout pin

defparam my_iobuf.io_standard = "3.3-V PCI";

defparam my_iobuf.current_strength = "minimum current";

defparam my_iobuf.slow_slew_rate = "on";

defparam my_iobuf.location = "iobank_1";

Example 2–8 shows a VHDL component declaration for an ALT_IOBUF

primitive instantiation.

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 55 56

Pas de commentaire

Altera Designing With Low-Level Primitives Manuel d'utilisateur Page 30