Altera Designing With Low-Level Primitives Manuel d'utilisateur télécharger pdf (Page 46)

2–24 Altera Corporation

Designing with Low-Level Primitives User Guide April 2007

Primitives

Example 2–15 shows an example of a Verilog HDL primitive

instantiation, and Example 2–16 shows a VHDL example of an

ALT_BIDIR_DIFF component declaration.

Example 2–15. ALT_BIDIR_DIFF Primitive Instantiation, Verilog HDL

module ddio_top (aset, combout, datain_h, datain_l, inclock, sclr, oe,

outclock, bidir, bidir_n );

input aset;

input sclr;

input datain_h;

input datain_l;

input inclock;

input oe;

input outclock;

output combout;

inout bidir;

inout bidir_n;

wire tmp_oe;

wire tmp_padio;

//myddio_bidir is an instance of the altddio_bidir megafunction

myddio_bidir sample_ddio ( .aset(aset),

.combout(combout),

.datain_h (datain_h),

.datain_l(datain_l),

.inclock(inclock),

.oe(oe),

.outclock(outclock),

.padio(tmp_padio),

.oe_out_port(tmp_oe),

.sclr(sclr)

);

ALT_BIDIR_DIFF my_bidir (.bidirin (tmp_padio), .oe (tmp_oe), .io (bidir),

.iobar (bidir_n));

endmodule

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 55 56

Pas de commentaire

Altera Designing With Low-Level Primitives Manuel d'utilisateur Page 46