Altera DDR3 SDRAM High-Performance Controller and ALTMEMP Manuel d'utilisateur télécharger pdf (Page 5)

Chapter 15: Introduction to ALTMEMPHY IP 15–5

Features

November 2012 Altera Corporation External Memory Interface Handbook

Volume 3: Reference Material

Configurable command look-ahead bank management with

in-order reads and writes

Additive latency vv

Support for arbitrary Avalon burst length vv

Built-in flexible memory burst adapter vv

Configurable Local-to-Memory address mappings vv

Optional run-time configuration of size and mode register

settings, and memory timing

Partial array self-refresh (PASR) vv

Support for industry-standard DDR3 SDRAM devices

Optional support for self-refresh command vv

Optional support for user-controlled power-down command vv

Optional support for automatic power-down command with

programmable time-out

Optional support for auto-precharge read and auto-precharge

write commands

Optional support for user-controller refresh vv

Optional multiple controller clock sharing in SOPC Builder Flow

Integrated error correction coding (ECC) function 72-bit vv

Integrated ECC function, 16, 24, and 40-bit vv

Support for partial-word write with optional automatic error

correction

SOPC Builder ready

Support for OpenCore Plus evaluation vv

IP functional simulation models for use in Altera-supported VHDL

and Verilog HDL simulator

Notes to Table 15–5:

(1) HPC II supports additive latency values greater or equal to t

RCD

-1, in clock cycle unit (t

(2) This feature is not supported with DDR3 SDRAM with leveling

Table 15–5. Feature Support (Part 2 of 2)

Feature DDR and DDR2 DDR3

1 2 3 4 5 6 7 8 9 10

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Altera DDR3 SDRAM High-Performance Controller and ALTMEMP Manuel d'utilisateur Page 5