Altera Cyclone V GT FPGA Development Board Manuel d'utilisateur Page 64
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- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 13
- FPGA Configuration 19
- Figure 2–3. JTAG Chain 20
- Note to Table 2–6: 21
- Figure 2–4. PFL Configuration 22
- Status Elements 23
- Setup Elements 24
- CPU Reset Push Button 25
- Clock Circuitry 26
- Off-Board Clock Input/Output 28
- General User Input/Output 29
- General LEDs 30
- HSMC LEDs 31
- PCI Express LEDs 31
- Components and Interfaces 32
- 10/100/1000 Ethernet 34
- SDI Channel (Optional) 42
- SDI Video Output 43
- SDI Video Input 44
- DDR3 SDRAM 45
- FLASH_RESETN AB16 2.5-V Reset 56
- Power Supply 57
- Power Distribution System 58
- Power Measurement 59
- 3. Board Components Reference 61
- Notes to Table 3–2: 63
- Note to Table: 65
- Typographic Conventions 66
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