Altera Cyclone V GT FPGA Development Board Manuel d'utilisateur télécharger pdf (Page 52)

2–44 Chapter 2: Board Components

Memory

Cyclone V GT FPGA Development Board September 2014 Altera Corporation

Reference Manual

DDR3B_A12

T31 1.5-V SSTL Class I Address bus

DDR3B_A13

T30 1.5-V SSTL Class I Address bus

DDR3B_BA0

J31 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

N29 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

P27 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

N27 1.5-V SSTL Class I Row address select

DDR3B_CKE

AF32 1.5-V SSTL Class I Column address select

DDR3B_CLK_P

R30

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CLK_N

R29

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CSN

V27 1.5-V SSTL Class I Chip select

DDR3B_DM2

AC34 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM3

W34 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ16

AD34 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ17

AC33 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ18

AG34 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ19

AB33 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ20

AE33 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ21

V32 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ22

AH34 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ23

W32 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ24

U29 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ25

V34 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ26

U34 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ27

AA33 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ28

R34 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ29

Y33 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ30

P34 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ31

U28 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQS_P2

V24

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

DDR3B_DQS_N2

V23

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 2

DDR3B_DQS_P3

U24

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 3

DDR3B_DQS_N3

U25

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 3

DDR3B_ODT

AA32 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

Y32 1.5-V SSTL Class I Row address select

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 6)

Board Reference

Schematic

Signal Name

Cyclone V GT

Pin Number

I/O Standard Description

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 65 66

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Altera Cyclone V GT FPGA Development Board Manuel d'utilisateur Page 52

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