
Chapter 2: Board Components 2–41
Memory
September 2014 Altera Corporation Cyclone V GT FPGA Development Board
Reference Manual
N7
DDR3A_A12
AM13 1.5-V SSTL Class I Address bus
T3
DDR3A_A13
AN13 1.5-V SSTL Class I Address bus
M2
DDR3A_BA0
AN16 1.5-V SSTL Class I Bank address bus
N8
DDR3A_BA1
AN17 1.5-V SSTL Class I Bank address bus
M3
DDR3A_BA2
AP17 1.5-V SSTL Class I Bank address bus
K3
DDR3A_CASN
AP15 1.5-V SSTL Class I Row address select
K9
DDR3A_CKE
AP26 1.5-V SSTL Class I Column address select
J7
DDR3A_CLK_P
AA18
Differential 1.5-V SSTL
Class I
Differential output clock
K7
DDR3A_CLK_N
AA17
Differential 1.5-V SSTL
Class I
Differential output clock
L2
DDR3A_CSN
AA16 1.5-V SSTL Class I Chip select
E7
DDR3A_DM4
AL30 1.5-V SSTL Class I Write mask byte lane
E3
DDR3A_DQ32
AH23 1.5-V SSTL Class I Data bus byte lane 4
F7
DDR3A_DQ33
AG23 1.5-V SSTL Class I Data bus byte lane 4
F2
DDR3A_DQ34
AN32 1.5-V SSTL Class I Data bus byte lane 4
F8
DDR3A_DQ35
AN29 1.5-V SSTL Class I Data bus byte lane 4
H3
DDR3A_DQ36
AK25 1.5-V SSTL Class I Data bus byte lane 4
H8
DDR3A_DQ37
AJ25 1.5-V SSTL Class I Data bus byte lane 4
G2
DDR3A_DQ38
AK28 1.5-V SSTL Class I Data bus byte lane 4
H7
DDR3A_DQ39
AM30 1.5-V SSTL Class I Data bus byte lane 4
F3
DDR3A_DQS_P4
AC21
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 4
G3
DDR3A_DQS_N4
AD21
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 4
K1
DDR3A_ODT
AN21 1.5-V SSTL Class I On-die termination enable
J3
DDR3A_RASN
AP14 1.5-V SSTL Class I Row address select
T2
DDR3A_RESETN
AJ22 1.5-V SSTL Class I Reset
L3
DDR3A_WEN
AN12 1.5-V SSTL Class I Write enable
L8
DDR3A_ZQ03
— 1.5-V SSTL Class I ZQ impedance calibration
Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)
Board Reference
Schematic
Signal Name
Cyclone V GT
Pin Number
I/O Standard Description
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