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Table 7-5: ALTFP_MULT Megafunction Parameters
Parameter Name Type Required Description
WIDTH_EXP Integer No Specifies the value of the exponent. If this
parameter is not specified, the default is 8.
The bias of the exponent is always 2
(WIDTH_
EXP - 1)
-1 (that is, 127 for the single-
precision format and 1023 for the double-
precision format). WIDTH_EXP must be 8
for the single-precision format or a
minimum of 11 for the double-precision
format and the single-extended precision
format. WIDTH_EXP must less than WIDTH_
MAN. The sum of WIDTH_EXP and WIDTH_
MAN must be less than 64.
WIDTH_MAN
Integer No Specifies the value of the mantissa. If this
parameter is not specified, the default is
23. When WIDTH_EXP is 8 and the floating-
point format is single-precision, the
WIDTH_MAN value must be 23; otherwise,
the value of WIDTH_MAN must be a
minimum of 31. The WIDTH_MAN value
must always be greater than the WIDTH_
EXP value. The sum of WIDTH_EXP and
WIDTH_MAN must be less than 64.
DEDICATED_MULTIPLIER_ CIRCUITRY String No Specifies whether to use dedicated
multiplier circuitry. Values are AUTO, YES,
or NO. If this parameter is not specified, the
default is AUTO. If a device does not have
dedicated multiplier circuitry, the
DEDICATED_MULTIPLIER_CIRCUITRY
parameter has no effect and defaults to NO.
PIPELINE Integer No Specifies the number of clock cycles
needed to produce the multiplied result.
Values are 5, 6, 10, and 11. If this
parameter is not specified, the default is 5.
ALTFP_MULT Signals
Table 7-6: ALTFP_MULT IP Core Input Signals
Port Name Required Description
clock Yes Clock input to the IP core.
clk_en No Clock enable. Allows multiplication to take place when asserted high.
When signal is asserted low, no multiplication occurs and the outputs
remain unchanged.
UG-01058
2014.12.19
ALTFP_MULT Signals
7-5
ALTFP_MULT IP Core
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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