Altera Floating-Point Manuel d'utilisateur Page 20
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Figure 1-9: Single-Precision Representation
This figure shows a single-precision representation.
S E M
31 30 23 22 0
Double-Precision Format
The double-precision format contains the following binary patterns:
• The MSB holds the sign bit.
• The next 11 bits hold the exponent bits.
• 52 LSBs hold the mantissa.
The total width of a floating-point number in the double-precision format is 64 bits. The bias for the
double-precision format is 1023.
Figure 1-10: Double-Precision Representation
This figure shows a double-precision representation.
S E M
63 62 52 51 0
Single-Extended Precision Format
The single-extended precision format contains the following binary patterns:
• The MSB holds the sign bit.
• The exponent and mantissa fields do not have fixed widths.
• The minimum exponent field width is 11 bits and must be less than the width of the mantissa field.
• The width of the mantissa field must be a minimum of 31 bits.
The sum of the widths of the sign bit, exponent field, and mantissa field must be a minimum of 43 bits
and a maximum of 64 bits. The bias for the single-extended precision format is unspecified in the
IEEE-754 standard. In these IP cores, a bias of 2
(
WIDTH_EXP–1
)
–1 is assumed for the single-extended
precision format.
Special Case Numbers
The following table lists the special case numbers defined by the IEEE-754 standard and the data bit
representations.
Table 1-4: Special Case Numbers in IEEE-754 Representation
Meaning Sign Field Exponent Field Mantissa Field
Zero Don’t care All 0’s All 0’s
Positive Denormalized 0 All 0’s Non-zero
1-14
Double-Precision Format
UG-01058
2014.12.19
Altera Corporation
About Floating-Point IP Cores
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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