Altera Quartus II Settings File Manuel d'utilisateur télécharger pdf (Page 90)

EXTRACT_VHDL_STATE_MACHINES

Allows the Compiler to extract state machines from VHDL Design Files. The Compiler optimizes state

machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler

extracts and optimizes state machines in VHDL Design Files as regular logic.

Type

Boolean

Device Support

This setting can be used in projects targeting any Altera device family.

Notes

This assignment is included in the Analysis & Synthesis report.

Syntax

set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES <value>

Default Value

Example

set_global_assignment -name extract_vhdl_state_machines off

See Also

State Machine Processing Extract Verilog State Machines

EXTRACT_VHDL_STATE_MACHINES

MNL-Q21005

2015.05.04

Altera Corporation

Quartus Settings File Reference Manual

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Altera Quartus II Settings File Manuel d'utilisateur Page 90