Altera Parallel Flash Loader IP Manuel d'utilisateur télécharger pdf (Page 55)

Example 5: Single Quad SPI Flash

• Single quad SPI flash configuration time calcualtion

.rbf size for EP2S15 = 577KB = 590,848 Bytes

Configuration mode = FPP without data compression or encryption

Flash access mode = Burst Mode

Flash data bus width = 4 bits (only one quad SPI flash is used)

Flash access time = 100 ns

PFL input Clock = 100 MHz

DCLK ratio = 2

• Use the following formulas in this calculation:

Cflash = 4

Ccfg = 2

Coverhead = 48

Total Clock Cycles = Coverhead + max (Cflash, Ccfg)*N

Total Configuration Time = Total Clock Cycle/ PFL Input Clock

• Substitute these values in the following formulas:

Cflash = 4

Ccfg = 2

Coverhead = 48

Total Clock Cycles = 48 + 4 * 590848 = 2363440

Total Configuration Time at 100 MHz = 2363440 / 100 × 106 = 23.63 ms

Example 6: Four Cascaded Quad SPI Flashes

• Four cascaded quad SPI flashes configuration time calcualtion:

.rbf size for EP2S15 = 577KB = 590,848 Bytes

Configuration mode = FPP without data compression or encryption

Flash access mode = Burst Mode

Flash data bus width = 16 bits (total bus width for four quad SPI flashes)

Flash access time = 100 ns

PFL input Clock = 100 MHz

DCLK ratio = 2

The configuration time calculation for four cascaded quad SPI flash is identical to the configura‐

tion time calculation for CFI flash with 16 bit flash data width.

UG-01082

2015.01.23

Specifications

Parallel Flash Loader IP Core User Guide

Altera Corporation

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Altera Parallel Flash Loader IP Manuel d'utilisateur Page 55