Altera Parallel Flash Loader IP Manuel d'utilisateur télécharger pdf (Page 2)

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is

<home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

Device Support

This user guide focuses on implementing the PFL IP core in an Altera CPLD. The PFL IP core supports all

Altera FPGAs. You can implement the PFL IP core in an Arria

, Cyclone

, or Stratix

device family

FPGA to program flash memory or to configure other FPGAs.

Related Information

AN478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software

Provides more information about using the FPGA-based PFL IP core to program a flash memory device.

Supported Flash Memory Devices

The Quartus II software generates the PFL IP core logic for the flash programming bridge and FPGA

configuration.

Table 1: CFI Flash Memory Devices Supported by PFL IP Core

If your CFI device is not in the following table, but is compatible with an Intel or Spansion CFI flash device, Altera

recommends selecting Define CFI Flash Device in the Quartus II software.

Manufacturer Product Family Data Width Density (Megabit) Device Name

(1)(2)

Micron

C3 16

8 28F800C3

16 28F160C3

32 28F320C3

64 28F640C3

8 or 16

32 28F320J3

64 28F640J3

128 28F128J3

16 256 JS29F256J3

(1)

Spansion has discontinued the Spansion S29GL-N flash memory device family. Altera does not recommend

using this flash memory device. For more information about an alternative recommendation, see related

information.

(2)

The PFL IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory

devices, the PFL IP core supports top, bottom, and symmetrical blocks of flash memory devices.

Device Support

UG-01082

2015.01.23

Altera Corporation

Parallel Flash Loader IP Core User Guide

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