Altera Mentor Verification IP Altera Edition AMBA AXI4-St Manuel d'utilisateur Page 57
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SystemVerilog Monitor BFM
Monitor BFM Configuration
Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
57
April 2014
Table 5-1 describes the parameter names for the data and ID signals and their default values.
A monitor BFM has configuration fields that set with the set_config() function to configure
timeout factors, setup and hold times, and so on. You get the value of a configuration field with
the get_config() function. Table 5-2 describes the configuration fields.
Table 5-1. Monitor BFM Signal Width Parameters
Signal Width Parameter Description
AXI4_ID_WIDTH ID signal width in bits. This applies to the TID signal.
Refer to the AMBA AXI4-Stream Protocol Specification
for more details. Default: 18.
AXI4_USER_WIDTH User data signal width in bits. This applies to the TUSER
signal. Refer to the AMBA AXI4-Stream Protocol
Specification for more details. Default: 8.
AXI4_DEST_WIDTH Destination routing signal width in bits. This applies to
the TDEST signal. Refer to the AMBA AXI4-Stream
Protocol Specification for more details. Default: 18.
AXI4_DATA_WIDTH Data signal width in bits. This applies to the TDATA
signal. Refer to the AMBA AXI4-Stream Protocol
Specification for more details. Default: 1024.
Table 5-2. Monitor BFM Configuration
Configuration Field Description
Timing Variables
AXI4STREAM_CONFIG_SETUP_TIME The setup-time prior to the active
edge of ACLK, in units of
simulator time-steps for all
signals.
1
Default: 0.
AXI4STREAM_CONFIG_HOLD_TIME The hold-time after the active
edge of ACLK, in units of
simulator time-steps for all
signals.
1
Default: 0.
AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay permitted
between the individual transfer
transactions in clock cycles.
Default: 10000.
AXI4STREAM_CONFIG_MAX_LATENCY_TVALID_
ASSERTION_TO_TREADY
The maximum delay permitted
between the assertion of
TVALID to the assertion of
TREADY. Default: 10000.
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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