Altera Mentor Verification IP Altera Edition AMBA AXI4-St Manuel d'utilisateur Page 214
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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
214
VHDL Master and Slave Test Programs
VHDL Master BFM Code Example
April 2014
end master_test_program;
architecture master_test_program_a of master_test_program is
begin
process
variable trans: integer;
variable byte_count : integer := AXI4_DATA_WIDTH/8;
variable transfer_count : integer;
variable k : integer;
variable m : integer;
begin
wait_on(AXI4STREAM_RESET_POSEDGE, index, axi4stream_tr_if_0(index));
wait_on(AXI4STREAM_CLOCK_POSEDGE, index, axi4stream_tr_if_0(index));
--************************
-- Traffic generation: **
--************************
-- 10 x packet with
-- Number of transfer = i % 10. Values : 1, 2 .. 10
-- id = i % 15. Values 0, 1, 2 .. 14
-- dest = i %20. Values 0, 1, 2 .. 19
for i in 0 to 9 loop
transfer_count := (i mod 10) + 1;
create_master_transaction(transfer_count, trans, index,
axi4stream_tr_if_0(index));
set_id(i mod 15, trans, index, axi4stream_tr_if_0(index));
set_dest(i mod 20, trans, index, axi4stream_tr_if_0(index));
for j in 0 to ((transfer_count * byte_count) - 1) loop
set_data(i + j, j, trans, index, axi4stream_tr_if_0(index));
if(((i + j) mod 5) = 0) then
set_byte_type(AXI4STREAM_NULL_BYTE, j, trans, index,
axi4stream_tr_if_0(index));
elsif(((i + j) mod 5) = 1) then
set_byte_type(AXI4STREAM_POS_BYTE, j, trans, index,
axi4stream_tr_if_0(index));
else
set_byte_type(AXI4STREAM_DATA_BYTE, j, trans, index,
axi4stream_tr_if_0(index));
end if;
end loop;
execute_transaction(trans, index, axi4stream_tr_if_0(index));
end loop;
-- 10 x packet at transfer level with
-- Number of transfer = i % 10. Values : 1, 2 .. 10
-- id = i % 15. Values 0, 1, 2 .. 14
-- dest = i %20. Values 0, 1, 2 .. 19
for i in 0 to 9 loop
transfer_count := (i mod 10) + 1;
create_master_transaction(transfer_count, trans, index,
axi4stream_tr_if_0(index));
set_id(i mod 15, trans, index, axi4stream_tr_if_0(index));
set_dest(i mod 20, trans, index, axi4stream_tr_if_0(index));
m := 0;
while(m < transfer_count) loop
k := 0;
while(k < byte_count) loop
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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