Altera Mentor Verification IP Altera Edition AMBA AXI4-St Manuel d'utilisateur Page 157
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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
157
April 2014
Chapter 10
VHDL Monitor BFM
This section provides information about the VHDL monitor BFM. It has an API that contains
procedures to configure the BFM and to access the dynamic Transaction Record during the life
of the transaction.
Inline Monitor Connection
The connection of a monitor BFM to a test environment differs from that of a master and slave
BFM. It is wrapped within an inline monitor interface and connected inline between a master
and slave, as shown in Figure 10-1. It has separate master and slave ports, and monitors protocol
traffic between a master and slave. The monitor has access to all the facilities provided by the
monitor BFM.
Figure 10-1. Inline Monitor Connection Diagram
Monitor BFM Protocol Support
The monitor BFM supports the full AMBA AXI4-Stream protocol.
Monitor Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA
AXI4-Stream Protocol Specification chapter, which you can reference for details of the
following monitor BFM API timing and events.
The AMBA AXI4-Stream Protocol Specification does not define any timescale or clock period
with signal events sampled and driven at rising ACLK edges. Therefore, the monitor BFM does
SlaveMaster
Inline monitor
Master portSlave port
Monitor
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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