Altera IP Compiler for PCI Express Manuel d'utilisateur télécharger pdf (Page 306)

16–18 Chapter 16: Qsys Design Example

Preparing the Design for Compilation

IP Compiler for PCI Express User Guide August 2014 Altera Corporation

Adding Files to your Quartus II Project

To complete your design example, you must add the wrapper file to your project. To

ensure the project configures and runs correctly on hardware, your project also

requires FPGA pin assignments and timing constraints for the top-level signals.

Altera provides a Synopsys Design Constraints File (.sdc) and a Tcl file (.tcl) that

include these assignments for an EP4SGX230KF40C2 device. In addition, you must

include the altgxb_reconfig and GPLL files. You can generate these two files by

creating an altgxb_reconfig instance and a GPLL instance in the parameter editor, or

you can use the Altera-provided Verilog HDL files that are already generated with the

correct names to connect with the Altera-provided wrapper file.

To add the files to your Quartus II project, follow these steps:

1. Copy the following files from <installation_directory>/ip/altera/altera_pcie/

altera_pcie_avmm/example_designs/s4gx_gen1x8 to your project directory:

■ altgxb_reconfig.v

■ gpll.v

■ s4gx_gen1x8_qsys_top.sdc

■ s4gx_gen1x8_qsys_top.tcl

■ s4gx_gen1x8_qsys_top.v

2. In the Quartus II software, open the s4gx_gen1x8_qsys_top.qpf project in which

you generated your design example Qsys system.

3. On the Assignments menu, click Settings.

4. In the Category panel, click Files.

5. Browse to each of the following files in the Quartus II project directory and click

Add:

■ altgxb_reconfig.v

■ gpll.v

■ s4gx_gen1x8_qsys_top.sdc

■ s4gx_gen1x8_qsys_top.tcl

■ s4gx_gen1x8_qsys_top.v

■ hip_s4gx_gen1x8_qsys/synthesis/hip_s4gx_gen1x8_qsys.qip

■ hip_s4gx_gen1x8_qsys/synthesis/submodules/altera_pci_express.sdc

6. Click Apply.

7. To confirm that the wrapper file is added to your project, follow these steps:

a. In the Quartus II software, in the Project Navigator panel, click the

s4gx_en1x8_qsys_top entity. Verilog HDL code displays in the Quartus II text

editor.

b. Open the s4gx_gen1x8_qsys_top.v file in a text editor.

c. Confirm that the code in the Quartus II text editor is the code in the

s4gx_gen1x8_qsys_top.v file.

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Altera IP Compiler for PCI Express Manuel d'utilisateur Page 306