Altera FFT MegaCore Function Manuel d'utilisateur Page 1

FFT IP CoreUser GuideSubscribeSend FeedbackUG-FFT2014.12.15101 Innovation DriveSan Jose, CA 95134www.altera.com

DeviceParametersALMDSPBlocksMemory RegistersfMAX(MHz)Type Length Engines M10K M20K PrimarySecondaryCycloneVBufferedBurst4,096 4 4,576 24 59 -- 10,980

DeviceParametersALMDSPBlocksMemory RegistersfMAX(MHz)Type Length Engines M10K M20K PrimarySecondaryCycloneVBurstSingleOutput4,096 1 695 2 19 -- 1,540

DeviceParametersALMDSPBlocksMemory RegistersfMAX(MHz)Type Length Engines M10K M20K PrimarySecondaryStratix VBufferedBurst256 1 1,546 6 -- 16 3,959 110

DeviceParametersALMDSPBlocksMemory RegistersfMAX(MHz)Type Length Engines M10K M20K PrimarySecondaryStratix VBurstSingleOutput1,024 1 652 2 -- 4 1,553

DeviceParametersALMDSPBlocksMemory RegistersfMAX(MHz)Type Length Engines M10K M20K PrimarySecondaryStratix VVariableStreaming4,096 — 2,924 18 -- 23 6,

FFT IP Core Getting Started22014.12.15UG-FFTSubscribeSend FeedbackInstalling and Licensing IP CoresThe Altera IP Library provides many useful IP core

OpenCore Plus evaluation supports the following two operation modes:• Untethered—run the design containing the licensed IP for a limited time.• Tether

Figure 2-2: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target d

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Figure 2-4: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

ContentsAbout This IP Core...1-1Altera DSP IP Core Features

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

Figure 2-5: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

Related InformationUsing MegaCore Functions chapter in the DSP Builder Handbook.UG-FFT2014.12.15DSP Builder Design Flow2-9FFT IP Core Getting StartedA

FFT IP Core Functional Description32014.12.15UG-FFTSubscribeSend FeedbackFixed Transform FFTsThe buffered, burst, and streaming FFTs use a radix-4 dec

Fixed-Point Variable Streaming FFTsFixed point variable streaming FFTs implements a radix-22 single delay feedback. It is similar to radix-2single del

Table 3-1: Input and Output Order OptionsInput Order OutputOrderMode CommentsNatural Bit reversedEngine-onlyRequires minimum memory andminimum latency

Figure 3-1: Quad-Output FFT Engine ROM0FFT EngineH[k,0]H[k,1]H[k,2]H[k,3]G[k,0]G[k,1]G[k,2]G[k,3]x[k,0]x[k,1]x[k,2]x[k,3]-j-1j-1-1j-1-jRAMA1RAMA0RAMA2

Figure 3-2: Single-Output FFT EngineH[k,m]G[k,0]G[k,1]G[k,2]G[k,3]x[k,0]x[k,1]x[k,2]x[k,3]-j-1j-1-1j-1-jRAMRAMROMFFT EngineBFPUI/O Data FlowStreaming

Figure 3-3: FFT Streaming Data Flow Simulation Waveformclkreset_nsink_validsink_readysink_sopsink_eopinversesink_realsink_imagsource_realsource_imagso

Block Floating Point Scaling...4-1Possible Exponent Values...

When the FFT completes the transform of the input block, it asserts source_valid and outputs thecomplex transform domain data block in natural order.

fftpts Transform Size00001000000 64Changing DirectionTo change direction on a block-by-block basis:1. Assert or deassert inverse (appropriately) simul

reverse I/O order option is Bit Reverse Order. If you select Floating Point, the FFT variation implementsthe mixed radix-4/2 algorithm and the reverse

Figure 3-7: Dynamically Changing the FFT Sizeclockreset_nsink_validsink_readysink_sopsink_eopinversesink_realsink_imagsource_realsource_imagsource_rea

Figure 3-9: Data Flow—Engine with Bit-Reversal or Digit-Reversal Modeclkreset_nsink_validsink_readysink_sopsink_eopsink_realsink_imagsource_realsource

Figure 3-11: FFT Buffered Burst Data Flow Output Flow Controlclksource_realtsource_imagsource_expsource_readymaster_source_validsource_sopsource_eopEX

Example 3-2: FFT Buffered Burst Data Flow Simulation Waveformclkreset_nsink_vaildsink_readysink_sopsink_eopinversesink_realsink_imagsource_realsource_

Figure 3-12: FFT Burst Data Flow Simulation Waveform-47729 271-47729 271EXP0EXP1EXP2clkreset_nsink_validsink_readysink_sopsink_eopinversesink_realsink

Parameter Value DescriptionI/O Data Flow StreamingVariable StreamingBuffered BurstBurstIf you select Variable Streaming and FloatingPoint, the precisi

Parameter Value DescriptionDSP Block ResourceOptimizationOn or Off Turn on for multiplier structure optimizations.These optimizations use different DS

About This IP Core12014.12.15UG-FFTSubscribeSend FeedbackAltera DSP IP Core Features• Avalon® Streaming (Avalon-ST) interfaces• DSP Builder ready• Tes

FFT IP Core Avalon-ST SignalsTable 3-6: Avalon-ST SignalsSignal Name DirectionAvalon-ST Type Size Descriptionclk Input clk 1 Clock signal that clocks

Signal Name DirectionAvalon-ST Type Size Descriptionsource_eop Output endofpacket 1 Marks the end of the outgoing FFTframe. Only valid when source_val

Component Specific SignalsThe component specific signals.Table 3-7: Component Specific Signals Signal Name DirectionSize Descriptionfftpts_inInput log

Block Floating Point Scaling42014.12.15UG-FFTSubscribeSend FeedbackBlock-floating-point (BFP) scaling is a trade-off between fixed-point and full floa

After every pass through a radix-2 or radix-4 engine in the FFT core, the addition and multiplicationoperations cause the data bits width to grow. In

N PSingle Output Engine Quad Output EngineMax (2) Min (2) Max (2) Min (2)2,048 6 –17 3 –16 04,096 6 –18 2 –17 –18,192 7 –20 4 –19 116,384 7 –21 3

full_range_real_out[25:0] <= {real_in[15:0],10'b0}; full_range_imag_out[26] <= {imag_in[15]}; full_range_imag_out[

Figure 4-1: Scaling of Input Data Sample = 0x5000Unity Gain in an IFFT+FFT PairGiven sufficiently high precision, such as with floating-point arithmet

Figure 4-2: Derivation to Achieve IFFT/FFT Pair Unity Gain IFFT x0 X0 = IFFT(x0) = N1× IFFTa (x0) = N1× data1 × 2–exp1 FFT x0 = F

Document Revision History52014.12.15UG-FFTSubscribeSend FeedbackFFT IP Core User Guide revision history.Date Version Changes Made2014.12.15 14.1• Adde

General DescriptionThe FFT IP core is a high performance, highly-parameterizable Fast Fourier transform (FFT) processor.The FFT IP core implements a c

Date Version Changes MadeNovember201313.1• Added more information to variable streaming I/O dataflow.• Removed device support for following devices:•

Altera® offers the following device support levels for Altera IP cores:• Preliminary support—Altera verifies the IP core with preliminary timing model

Item DescriptionVendor ID 6AF7Performance and Resource UtilizationTable 1-3: Performance and Resource UtilizationTypical performance using the Quartus

DeviceParametersALMDSPBlocksMemory RegistersfMAX(MHz)Type Length Engines M10K M20K PrimarySecondaryArriaVBurstQuadOutput256 2 2,474 12 14 -- 5,768 233

DeviceParametersALMDSPBlocksMemory RegistersfMAX(MHz)Type Length Engines M10K M20K PrimarySecondaryArriaVVariableStreamingFloatingPoint1,024 — 11,195