Altera Device-Specific Power Delivery Network Manuel d'utilisateur

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Device-Specific Power Delivery Network (PDN) Tool
2.0 User Guide
2015.03.06
UG-01157
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This user guide provides a brief overview of the various tabs in the device-specific PDN tool 2.0. You can
quickly and accurately design a robust power delivery network with the PDN tool 2.0. This is done by
calculating an optimum number of capacitors that meet the target impedance requirements for a given
power supply.
Note: The PDN tool 2.0 only supports Microsoft Excel 2007 and newer, and either US or UK English
language.
Table 1: PDN Tool 2.0 Software Verification
Altera
®
has tested and verified that the PDN tool 2.0 is compatible with these platforms and software versions.
Operating System Excel Versions
Windows 8 (32-bit) 2007, 2010, 2013
Windows 8 (64-bit) 2010, 2013
Windows 7 (32-bit) 2007, 2010, 2013
Windows 7 (64-bit) 2010, 2013
Windows XP 2007, 2010
Overview
The Altera PDN tool 2.0 helps PCB designers estimate the number, value, and type of decoupling
capacitors needed to develop an efficient PCB decoupling strategy. It allows you to do this during the
early design phase, without going through extensive pre-layout simulations.
The PDN tool 2.0 is a Microsoft Excel-based spreadsheet that calculates an impedance profile based on
your input. For a given power supply, the spreadsheet only requires basic design information to calculate
the impedance profile and the optimum number of capacitors to meet the desired impedance target
(Z
TARGET
). Basic design information includes the board stackup, transient current information, and ripple
specifications, for example. The tool also provides device- and power rail-specific PCB decoupling cut-off
frequency (F
EFFECTIVE
). The results obtained through the PDN tool 2.0 are intended only as a preliminary
estimate and not as a specification. For an accurate impedance profile, Altera recommends a post-layout
simulation approach using any available EDA tool, such as Sigrity PowerSI, Ansoft SIWave, Cadence
Allegro PCB PI, and so on.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
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Résumé du contenu

Page 1 - 2.0 User Guide

Device-Specific Power Delivery Network (PDN) Tool2.0 User Guide2015.03.06UG-01157SubscribeSend FeedbackThis user guide provides a brief overview of th

Page 2 - PDN Circuit Topology

The available options are:• " " — Device rail does not connect to the power group.• x — Device rail connects to the power group.• x/related—

Page 3

The Die Noise Tolerance parameter has a pull-down menu with the following options:• Calculate• OverrideSome PDN tool variants allow you to add data fo

Page 4

1. Select the Plane_Cap tab in the PDN tool 2.0.2. Set the parameters to match your system, and notice that the Total planar capacitance and Totalshee

Page 5

Figure 6: Results Summary Section of the System_Decap TabRecommended Flow for Deriving Decoupling for FPGA System using the System_Decap TabTo use the

Page 6 - Tab Description

Figure 7: Stackup TabStackup DataThe Stackup Data section is where you enter board dimension data and other parameters, such as boardstackup settings,

Page 7 - System_Decap

Table 4: Full Stackup ButtonsButton Label DescriptionConstruct Stackup Populates the Full Stackup section to the number of layersdefined in the Stacku

Page 8

Figure 8: BGA_Via TabThe values in the Unit column indicate a unit value per one pair.Enter the layout-specific information such as via drill diameter

Page 9

Figure 9: Plane_Cap TabEnter the design specific information such as plane dimensions, plane configuration and the dielectricmaterial used in the Plan

Page 10 - Related Information

Figure 10: Cap Mount TabThe capacitor mounting calculation is based on the assumption that the decoupling capacitor is a two-terminal device. The capa

Page 11 - Send Feedback

Figure 11: X2Y_Mount TabEnter all the information relevant to your layout in the X2Y CAP Mounting Inductance table. The toolthen provides a mounting i

Page 12 - Spreading Section

The device families supported by the Altera device-specific PDN tool 2.0 are shown at the top of theRelease Notes tab and they include:• Arria® 10• Ar

Page 13 - 2015.03.06

Figure 12: Library TabYou can change each of the default values listed in the respective sections to meet the specific needs ofyour design.Two-Termina

Page 14 - Stackup Data

• 0201• 0402• 0603• 0805• 1206You also have the option to either modify the default values or enter your own commonly used customvalues in the Custom

Page 15 - Button Label Description

design. You can choose a Low value of effective spreading inductance if you have optimally designed yourPDN Network. Optimum PDN design involves imple

Page 16 - Plane_Cap

Figure 13: Enlarged_Graph TabDesign PCB Decoupling Using the PDN Tool 2.0PCB decoupling keeps PDN ZEFF smaller than ZTARGET with the properly chosen P

Page 17 - Cap_Mount

In the pre-layout phase of the design cycle when you do not have specific information about the boardstack-up and board layout, you can follow these i

Page 18 - X2Y_Mount

1. Enter the ESR, ESL, and Lmnt values for the capacitors listed in the Custom field.2. Enter the effective BGA via (loop) parasitics for the power su

Page 19

Figure 15: Enlarged Plot of ZEFFThe design is a decoupling example for a 10AX115R_F40 VCC power rail. Assume that the minimumvoltage supply is 0.9 V,

Page 20

The power regulators must be able to supply the total combined current requirements for each load on thesupply, but the decoupling capacitor selection

Page 21 - Bulk Capacitors

Realistic tool entry can make decoupling easier to achieve. The following factors affect the calculation ofZTARGET:• An increase in dynamic current re

Page 22 - Enlarged_Graph

For first order analysis, the VRM can be simply modeled as a series-connected resistor and inductor asshown above. The VRM has a very low impedence an

Page 23 - Pre-Layout Instructions

To accurately calculate the ZTARGET for any power rail, you must know the following information:• The maximum dynamic current change requirements for

Page 24

Rail Name (1)Voltage (V) Die NoiseTolerance (%)Dynamic CurrentChange (%)DescriptionVCCERAM 0.95 5 50 Programmable PowerTech AuxVCCBAT 1.2/1.5/1.8 5 10

Page 25

FEFFECTIVEAs previously illustrated, a capacitor reduces PDN impedance by providing a least-impedance routebetween power and ground. Impedance of a ca

Page 26

Tab DescriptionSystem_Decap The principal tab that allows you to decouple your system. Itdisplays by default when you launch the application. This tab

Page 27 - Troubleshooting Z

Device Selection Section1. Select the Family/Device using the pull-down list.2. Select your device from the Available Devices pull-down list.3. Select

Page 28 - Document Revision History

Figure 5: Power Rail Data and Power Sharing Scheme SectionThis configuration is an example of how this section of the spreadsheet should look. Every d

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