Altera Cyclone V SoC Manuel d'utilisateur télécharger pdf (Page 32)

5–14 Chapter 5: Board Test System

Using the Board Test System

Cyclone V SoC Development Kit November 2013 Altera Corporation

User Guide

XCVR, LVDS, CMOS

These groups displays the following XCVR, LVDS, CMOS status information during

the loopback test:

■ Data rate—Displays the current XCVR data rate in megabytes per second (MBps).

■ Freq—Displays the data rate frequency in MHz which is equivalent to Mbps.

■ Bits—Displays the number of bits transmitted since clicking Start.

■ Inserted errors—Displays the number of errors inserted by clicking Insert Error

button.

■ Detected errors—Displays the number of bit errors detected by the error checking

circuitry.

■ BER—Displays the bit error rate of the interface.

■ PLL lock—Displays Yes if the SDI PLL is locked.

■ Pattern Sync—Displays Yes if the receiver has detected the input data pattern.

■ Start— Starts the PRBS data test and begins to monitor and update screen with

live test results.

■ Stop—Stops the PRBS data test.

■ Insert Error—Inserts an error into a data stream that is detected by the receiver

when in loopback using the included video cable.

With the Insert Error, there are differences among the three ports:

XCVR—inserts 4 errors at 1 click due to 4 test control blocks in the design.

LVDS—inserts 3 errors at 1 click due to 3 test control block in the design.

CMOS—inserts 1 error at 1 click.

■ Clear—Clears the Detected errors counter.

■ PMA Setting—Opens the PMA settings window that allows for adjusting the

analog transceiver settings, such as output voltage, loopback settings, and

equalization.

The following settings are available for analysis:

■ Serial Loopback—Routes the selected TX output signal back to the RX input

signal on-chip to verify operation without using an external loopback board.

■ VOD—Specifies the voltage output (differential) of the transmitter buffer.

■ Pre-emphasis tap

■ Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter

buffer.

■ First post—Specifies the amount of pre-emphasis on the first post tap of the

transmitter buffer.

■ Second post—Specifies the amount of pre-emphasis on the second post tap

of the transmitter buffer.

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 43 44

Pas de commentaire

Altera Cyclone V SoC Manuel d'utilisateur Page 32