Altera Cyclone V SoC Development Board Manuel d'utilisateur Page 68
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- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 13
- FPGA Configuration 19
- Figure 2–3. JTAG Chain 20
- Note to Table 2–6: 22
- Figure 2–4. PFL Configuration 23
- FPGA Programming using EPCQ 24
- Board Settings DIP Switch 25
- JTAG Chain Control DIP Switch 26
- HPS Jumpers 27
- CPU Reset Push Button 27
- MAX V Reset Push Button 28
- Program Select Push Button 28
- User-Defined Push Buttons 28
- User-Defined DIP Switch 29
- User-Defined LEDs 29
- Clock Circuitry 30
- Off-Board Input/Output Clock 31
- PCI Express 32
- Components and Interfaces 33
- 10/100/1000 Ethernet (HPS) 34
- 10/100 Ethernet (FPGA) 36
- RS-232 UART (HPS) 42
- CAN Bus (HPS) 42
- Real-Time Clock (HPS) 43
- SPI Master 43
- C Interface 43
- SDI Video 44
- SDI Video Input 45
- DDR3 SDRAM (FPGA) 46
- DDR3 SDRAM (HPS) 49
- QSPI Flash (HPS) 53
- EPCQ Flash 54
- CFI Flash 54
- Micro SD Flash Memory 56
- C EEPROM 56
- Power Supply 57
- Power Distribution System 58
- Power Measurement 59
- 3. Board Components Reference 61
- Notes to Table 3–2: 63
- CE EMI Conformity Caution 64
- Note to Table: 66
- Visual Cue Meaning 67
- Typographic Conventions 68
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