Altera Cyclone V SoC Development Board Manuel d'utilisateur télécharger pdf (Page 46)

2–38 Chapter 2: Board Components

Memory

Cyclone V SoC Development Board November 2013 Altera Corporation

Reference Manual

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External Memory

Interface Handbook.

DDR3 SDRAM (FPGA)

The development board supports two 32Mx16x8 DDR3 SDRAM interface for very

high-speed sequential memory access. The 32-bit data bus comprises of two ×16

devices with a single address or command bus. This interface connects to the

dedicated HMC I/O banks on the bottom edge of the FPGA.

The DDR3 device shipped with this board are running at 400 MHz, for a total

theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is

800 MHz with a CAS latency of 9.

Table 2–32 lists the DDR3 SDRAM pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and

direction.

Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference

Schematic

Signal Name

Cyclone V SoC

Pin Number

I/O Standard Description

DDR3 x16 (U37)

DDR3_FPGA_A0

AJ14 1.5-V SSTL Class I Address bus

DDR3_FPGA_A1

AK14 1.5-V SSTL Class I Address bus

DDR3_FPGA_A2

AH12 1.5-V SSTL Class I Address bus

DDR3_FPGA_A3

AJ12 1.5-V SSTL Class I Address bus

DDR3_FPGA_A4

AG15 1.5-V SSTL Class I Address bus

DDR3_FPGA_A5

AH15 1.5-V SSTL Class I Address bus

DDR3_FPGA_A6

AK12 1.5-V SSTL Class I Address bus

DDR3_FPGA_A7

AK13 1.5-V SSTL Class I Address bus

DDR3_FPGA_A8

AH13 1.5-V SSTL Class I Address bus

DDR3_FPGA_A9

AH14 1.5-V SSTL Class I Address bus

DDR3_FPGA_A10

AJ9 1.5-V SSTL Class I Address bus

DDR3_FPGA_A11

AK9 1.5-V SSTL Class I Address bus

DDR3_FPGA_A12

AK7 1.5-V SSTL Class I Address bus

DDR3_FPGA_A13

AK8 1.5-V SSTL Class I Address bus

DDR3_FPGA_A14

AG12 1.5-V SSTL Class I Address bus

DDR3_FPGA_BA0

AH10 1.5-V SSTL Class I Bank address bus

DDR3_FPGA_BA1

AJ11 1.5-V SSTL Class I Bank address bus

DDR3_FPGA_BA2

AK11 1.5-V SSTL Class I Bank address bus

DDR3_FPGA_CASN

AH7 1.5-V SSTL Class I Row address select

DDR3_FPGA_CKE

AJ21 1.5-V SSTL Class I Column address select

DDR3_FPGA_CLK_P

AA14

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3_FPGA_CLK_N

AA15

Differential 1.5-V

SSTL Class I

Differential output clock

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 67 68

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Altera Cyclone V SoC Development Board Manuel d'utilisateur Page 46

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