Altera Arria V GX FPGA Manuel d'utilisateur télécharger pdf (Page 36)

6–14 Chapter 6: Board Test System

Using the Board Test System

Arria V GX FPGA Development Kit July 2012 Altera Corporation

User Guide

Port

The Port control allows you to specify which interface to test. The following port tests

are available:

■ Chip to Chip XCVR x8

■ SFP+ x1

■ SMA x1

PMA Setting

The PMA Setting button allows you to make changes to the PMA parameters that

affect the active transceiver interface. The following settings are available for analysis:

■ Serial Loopback—Routes signals from the receiver to the transmitter. Enter the

following values to enable the serial loopbacks:

= high speed serial transceiver signals to loopback on the board

= serial loopback

= reverse serial loopback pre-CDR

= reverse serial loopback post-CDR

■ VOD—Specifies the voltage output differential of the transmitter buffer.

■ Pre-emphasis tap

■ Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter

buffer.

■ First post—Specifies the amount of pre-emphasis on the first post tap of the

transmitter buffer.

■ Second post—Specifies the amount of pre-emphasis on the second post tap of

the transmitter buffer.

■ Equalizer—Specifies the setting for the receiver equalizer.

■ DC gain—Specifies the DC portion of the receiver equalizer.

Data Type

The Data type control specifies the type of data contained in the transactions. The

following data types are available for analysis:

■ PRBS7—Selects pseudo-random 7-bit sequences.

■ PRBS15—Selects pseudo-random 15-bit sequences.

■ PRBS23—Selects pseudo-random 23-bit sequences.

■ PRBS31—Selects pseudo-random 31-bit sequences.

■ HF1—highest frequency divide-by-2 data pattern "10101010"

■ HF2—next highest frequency divide-by-6 data pattern "111000111000"

■ HF3—second lowest frequency divide-by-22 data pattern

■ LF —lowest frequency divide by 33 data pattern

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 59 60

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Altera Arria V GX FPGA Manuel d'utilisateur Page 36