Altera Arria V GX FPGA Development Board Manuel d'utilisateur Page 88
- Page / 90
- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Dual FPGA 7
- 1–4 Chapter 1: Overview 8
- 1–6 Chapter 1: Overview 10
- Handling the Board 10
- 2. Board Components 11
- Board Overview 12
- I/O Resources 17
- II CPLD EPM2210 System 20
- II device (U2) 20
- Table 2–7 lists the MAX 24
- Configuration 25
- Figure 2–4. JTAG Chain 26
- Figure 2–5. PFL Configuration 28
- Status Elements 29
- Setup Elements 31
- JTAG Settings DIP Switch 32
- CPU Reset Push Button 33
- MAX II Reset Push Button 33
- Clock Circuitry 34
- FPGA development board 35
- Off-Board Clock Input/Output 37
- General User Input/Output 39
- User-Defined DIP Switches 40
- User-Defined LEDs 41
- HSMC User-Defined LEDs 42
- SDI Video Output/Input 44
- Components and Interfaces 47
- 10/100/1000 Ethernet 50
- SFP+ Module 59
- FMC Connector 60
- Bull's Eye Connector 67
- DDR3A for FPGA 1 68
- I/O setting and direction 69
- DDR3B/C for FPGA 2 73
- Power Supply 83
- Power Measurement 85
- Notes to Table 2–64: 87
- Info–2 Additional Information 90
- Typographic Conventions 90
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