Altera Arria V GX FPGA Development Board Manuel d'utilisateur télécharger pdf (Page 19)

Chapter 2: Board Components 2–9

MAX II CPLD EPM2210 System Controller

November 2013 Altera Corporation Arria V GX FPGA Development Board

Reference Manual

MAX II CPLD EPM2210 System Controller

The board utilizes the EPM2210 System Controller, an Altera MAX

II CPLD, for the

following purposes:

■ FPGA configuration from flash

■ Power consumption monitoring

■ Virtual JTAG interface for PC-based GUI

■ Control registers for clocks

■ Control registers for remote system update

Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality

and external circuit connections as a block diagram.

FMC — 16 —

Chip-to-chip bridge — 32 —

Total Transceivers:

Table 2–5. Arria V GX FPGA 2 Pin Count and Usage (Part 2 of 2)

Function I/O Standard I/O Count Special Pins

Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram

Information

Embedded

Blaster

MAX II CPLD

Power

Calculations

SLD-HUB

PFL

Power

Measurement

Results

Virtual-JTAG

A5GX

LTC2418

Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

Control

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 89 90

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Altera Arria V GX FPGA Development Board Manuel d'utilisateur Page 19