Altera Arria V GT FPGA Manuel d'utilisateur télécharger pdf (Page 36)

6–14 Chapter 6: Board Test System

Using the Board Test System

Arria V GT FPGA Development Kit November 2012 Altera Corporation

User Guide

■ PRBS23—Selects pseudo-random 23-bit sequences.

■ PRBS31—Selects pseudo-random 31-bit sequences.

■ HF1—highest frequency divide-by-2 data pattern 10101010.

■ HF2—next highest frequency divide-by-4 data pattern 1100110011001100.

■ HF3—second lowest frequency divide-by-8 data pattern 1111000011110000.

■ LF SMA, SFP, Bull’s Eye—lowest frequency divide-by-40 data pattern.

■ LF—Chip-to-chip divide-by-32 data pattern.

1 Settings HF1, HF2, HF3, LF are for transmit observation only.

Error Control

The Error control control displays data errors detected during analysis and allows

you to insert errors:

■ Detected errors—Displays the number of data errors detected in the hardware.

■ Inserted errors—Displays the number of errors inserted into the transmit data

stream.

■ Insert Error—Inserts a one-word error into the transmit data stream each time you

click the button. Insert Error is only enabled during transaction performance

analysis.

■ Clear—Resets the Detected errors and Inserted errors counters to zeros.

■ Word error rate—Detected word errors/total received words.

Loopback

These controls display current transaction performance analysis information collected

since you last clicked Start:

■ TX and RX performance bars—Show the percentage of maximum theoretical data

rate that the requested transactions are able to achieve.

■ Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per

second.

Start

The Start control initiates transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 57 58

Pas de commentaire

Altera Arria V GT FPGA Manuel d'utilisateur Page 36