Altera Arria V GT FPGA Development Board Manuel d'utilisateur télécharger pdf (Page 63)

Chapter 2: Board Components 2–53

Components and Interfaces

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

Figure 2–11 shows a diagram of the color coded Bull's Eye connections. Follow the

color code to make loopback connections. For example, connect purple to purple

(pins 17 to 21) for RX to TX loopback. The only pins not connected are pins 3 and 4.

1 You can order more cables from www.samtec.com and these cable systems can be

reused on other boards.

f For specific instructions on how to install the connector to the board and insert the

cables into the connector, refer to Samtec's web page regarding this system.

Table 2–30 lists the Bull’s eye connector pin assignments, signal names, and functions.

Figure 2–11. Bull’s Eye Connections

Table 2–30. Bull’s Eye Connector Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J16)

Schematic Signal Name

Arria V GT FPGA

Pin Number

I/O Standard Description

BULLSEYE_SMA_CLKN

— LVDS or 2.5-V Clock buffer

BULLSEYE_SMA_CLKP

— LVDS or 2.5-V Clock buffer

SMA_A_10G_RX_N0

G2 LVDS or 2.5-V Transceiver channel

SMA_A_10G_RX_N1

H38 LVDS or 2.5-V Transceiver channel

SMA_A_10G_RX_P0

G1 LVDS or 2.5-V Transceiver channel

SMA_A_10G_RX_P1

H39 LVDS or 2.5-V Transceiver channel

SMA_A_6G_RX_N2

C2 LVDS or 2.5-V Transceiver channel

SMA_A_6G_RX_P2

C1 LVDS or 2.5-V Transceiver channel

SMA_A_TX_L15_N

G36 LVDS or 2.5-V Transceiver channel

SMA_A_TX_L15_P

G37 LVDS or 2.5-V Transceiver channel

SMA_A_TX_R16_N

F4 LVDS or 2.5-V Transceiver channel

SMA_A_TX_R16_P

F3 LVDS or 2.5-V Transceiver channel

SMA_A_TX_R17_N

B4 LVDS or 2.5-V Transceiver channel

SMA_A_TX_R17_P

B3 LVDS or 2.5-V Transceiver channel

SMA_B_10G_RX_N1

H38 LVDS or 2.5-V Transceiver channel

1 2 ... 58 59 60 61 62 63 64 65 66 67 68 ... 85 86

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Altera Arria V GT FPGA Development Board Manuel d'utilisateur Page 63

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