Altera Arria V GT FPGA Development Board Manuel d'utilisateur Page 10
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- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Dual FPGA 7
- 1–4 Chapter 1: Overview 8
- 1–6 Chapter 1: Overview 10
- Handling the Board 10
- 2. Board Components 11
- Board Overview 12
- I/O Resources 16
- II CPLD EPM2210 System 19
- II device (U2) 19
- Configuration 24
- Figure 2–4. JTAG Chain 25
- Figure 2–5. PFL Configuration 27
- Status Elements 28
- Setup Elements 30
- CPU Reset Push Button 31
- MAX II Reset Push Button 31
- Configuration Push Button 31
- Clock Circuitry 32
- FPGA development board 33
- Off-Board Clock Input/Output 35
- General User Input/Output 37
- User-Defined LEDs 38
- Arria V GT FPGA pin numbers 39
- HSMC User-Defined LEDs 40
- SDI Video Output/Input 41
- Components and Interfaces 43
- 10/100/1000 Ethernet 46
- SFP+ Modules 55
- FMC Connector 56
- Bull's Eye Connector 62
- DDR3A for FPGA 1 64
- I/O setting and direction 65
- DDR3B/C for FPGA 2 69
- Power Supply 78
- Power Distribution System 79
- Power Measurement 80
- Notes to Table 2–37: 82
- 3. Board Components Reference 83
- Typographic Conventions 86
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