Altera Arria V GT FPGA Development Board Manuel d'utilisateur télécharger pdf (Page 32)

2–22 Chapter 2: Board Components

Clock Circuitry

Arria V GT FPGA Development Board December 2014 Altera Corporation

Reference Manual

Image Select Push Button

The program select push button,

PGM1_SEL

(S2), is an input to the MAX II CPLD

System Controller. The push button toggles the

PGM1_LED[2:0]

sequence that selects

which location in the flash memory is used to configure the FPGA. Refer to Table 2–6

for the

PGM1_LED[2:0]

sequence definitions.

Clock Circuitry

This section describes the board's clock inputs and outputs.

On-Board Oscillators

The development board includes fixed and programmable oscillators with a

frequency of 50-MHz, 100-MHz, 125-MHz, 148.5-MHz, 156.25-MHz, and 625-MHz.

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 85 86

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Altera Arria V GT FPGA Development Board Manuel d'utilisateur Page 32