Altera Arria II GX FPGA Development Board, 6G Edition Manuel d'utilisateur télécharger pdf (Page 40)

2–32 Chapter 2: Board Components

Components and Interfaces

Arria II GX FPGA Development Board, 6G Edition Reference Manual © July 2010 Altera Corporation

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as

various differential I/O standards including, but not limited to, LVDS, mini-LVDS,

and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to

either the generic single-ended pin-out or generic differential pin-out.

Table 2–36 lists the HSMC port A interface pin assignments, signal names, and

functions.

Table 2–36. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference Description

Schematic Signal

Name I/O Standard

Arria II GX

Device

Pin Number

J2.17 Transceiver TX bit 3 HSMA_TX_P3

1.5-V PCML

K31

J2.18 Transceiver RX bit 3 HSMA_RX_P3 L33

J2.19 Transceiver TX bit 3n HSMA_TX_N3 K32

J2.20 Transceiver RX bit 3n HSMA_RX_N3 L34

J2.21 Transceiver TX bit 2 HSMA_TX_P2 M31

J2.22 Transceiver RX bit 2 HSMA_RX_P2 N33

J2.23 Transceiver TX bit 2n HSMA_TX_N2 M32

J2.24 Transceiver RX bit 2n HSMA_RX_N2 N34

J2.25 Transceiver TX bit 1 HSMA_TX_P1 P31

J2.26 Transceiver RX bit 1 HSMA_RX_P1 R33

J2.27 Transceiver TX bit 1n HSMA_TX_N1 P32

J2.28 Transceiver RX bit 1n HSMA_RX_N1 R34

J2.29 Transceiver TX bit 0 HSMA_TX_P0 T31

J2.30 Transceiver RX bit 0 HSMA_RX_P0 U33

J2.31 Transceiver TX bit 0n HSMA_TX_N0 T32

J2.32 Transceiver RX bit 0n HSMA_RX_N0 U34

J2.33 Management serial data HSMA_SDA

2.5-V

J2.34 Management serial clock HSMA_SCL T1

J2.35 JTAG clock signal JTAG_TCK L24

J2.36 JTAG mode select signal JTAG_TMS N25

J2.37 JTAG data output JTAG_HSMA_TDO —

J2.38 JTAG data input JTAG_HSMA_TDI —

J2.39 Dedicated CMOS clock out HSMA_CLKOUT0 P10

J2.40 Dedicated CMOS clock in HSMA_CLKIN0 AP17

J2.41 Dedicated CMOS I/O bit 0 HSMA_D0 L1

J2.42 Dedicated CMOS I/O bit 1 HSMA_D1 R6

J2.43 Dedicated CMOS I/O bit 2 HSMA_D2 K1

J2.44 Dedicated CMOS I/O bit 3 HSMA_D3 M1

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 61 62

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Altera Arria II GX FPGA Development Board, 6G Edition Manuel d'utilisateur Page 40

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