Altera ALTDLL Manuel d'utilisateur Page 100
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 4: Functional Description 4–64
Design Example: Implementing Half-Rate DDR2 Interface in Stratix III Devices
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
Reading Data from the External Memory
The following sequence describes the transferring of data from the bidirectional DQ
pins to the FPGA core with various delay chain settings (refer to Figure 4–26 on
page 4–65):
1 The interface to the external memory has a throughput of 666.666 Mbps during the
read process.
1 In Figure 4–26, only the input paths are used; therefore,
bidir_dq_hr_oe_in[15:0] =16’b1 and dqs_hr_oe_in[1:0] =2’b1 from 5µs
onwards.
1. Each bit in the bidir_dq_io[7:0] pin is toggled with a 10-MHz data signal
from 5.25 µs to 5.45 µs. The pin behavior is represented in the waveform in groups
of 4-bit signals because the bidir_dq_io[0] input is connected to the
bidir_dq_hr_input_data_out[3:0] outputs.
2. The bidir_dq_io[0] pin is connected to the input delay chain.
3. The output bidir_dq_0_input_delay_chain_inst/dataout of the delay
chain is connected to the input of the DDIO_IN port, which is clocked by a
specialized DQS circuitry that uses the DLL.
4. The outputs (bidir_dq_0_ddio_in_inst/regouthi and
bidir_dq_0_ddio_in_inst/regoutlo) of the previous DDIO_IN ports are
channeled to two input phase alignment blocks, respectively. These input phase
alignment blocks are clocked at 333.333 MHz by the c2 clock output of the PLL.
5. The outputs of the two IPAs, bidir_dq_0_ipa_high_inst/dataout and
bidir_dq_0_ipa_low_inst/dataout, are channeled to a half-rate input
block, which is clocked by the IO_CLOCK_DIVIDER blocks.
6. The output bidir_dq_0_half_rate_input_inst/dataout[3:0] of this
block is then connected to the bidir_dq_hr_input_data_out[3:0] outputs.
7. The same data is propagated through the other bidirectional pins of
bidir_dq_io[7:1], which causes the
bidir_dq_hr_input_data_out[31:4] outputs to toggle in the same manner.
8. The throughput of the data in the output ports are at a half-rate of 166.666 MHz.
9. The input delay chain is enabled.
The bidir_dq_0_input_delay_chain_inst/datain and
bidir_dq_0_input_delay_chain_inst/dataout signals are not aligned,
which indicates that there is a delay on the input delay chain.
The same read sequence applies to reading data with different chain values
activated on the input delay chain. You can obtain the difference in the delay chain
values by analyzing the timing paths of the following signals:
■ bidir_dq_io[0]
■ bidir_dq_0_input_delay_chain_inst/datain
■ bidir_dq_0_input_delay_chain_inst/dataout
■ bidir_dq_0_ddio_in_inst/regouthi
■ bidir_dq_0_ddio_in_inst/regoutlo
- ALTDLL and ALTDQ_DQS 1
- Megafunctions User Guide 1
- UG-01032-5.0 2
- Contents 3
- 1. About these Megafunctions 5
- Features 6
- 2. Getting Started 7
- ALTOCT Megafunction 8
- Customized Controller Logic 8
- Simulate the Design 9
- Create Timing Constraints 9
- Adjust Constraints 10
- Generate the Megafunctions 11
- Settings Value 13
- Turned off 14
- Enable DQS delay chain 14
- 3. Parameter Settings 19
- [5..0] output port 20
- ALTDLL Parameter Editor 21
- ALTDQ_DQS Parameter Editor 23
- Reset/Config Ports 26
- ports on the megafunction 27
- — DQS_OFFSETCTRL_ 27
- inputs to be registered by 28
- signals of 28
- “DQ Input Path” on page 4–8 29
- 4. Functional Description 37
- ■ DQS Input Path 38
- ■ DQ Input Path 38
- ■ DQ Output/OE Path 38
- ■ DQS Output/OE Path 38
- ■ DQ/DQS OCT Path 38
- ALTDLL Megafunction 39
- ALTDQ_DQS Megafunction 40
- DQS Input Path 42
- DQ Input Path 44
- DQ Output/OE Path 46
- DQS Output/OE Path 48
- DQ/DQS OCT Path 50
- Delay Chains 51
- Deskew Delay Chains 52
- Note to Figure 4–13: 55
- Note to Figure 4–14: 55
- Note to Figure 4–15: 56
- Note to Figure 4–16: 56
- Note to Figure 4–17: 57
- DQS_CONFIG / IO_CONFIG Block 58
- ALTDLL Megafunction Ports 67
- ALTDQ_DQS Megafunction Ports 69
- DQ OE Path Megafunction Ports 78
- DQSn I/O Path Ports 79
- DQS_CONFIG/IO_CONFIG path 81
- RLDRAM interfaces 84
- Procedure 85
- 00 FF 00 FF 99
- ■ bidir_dq_io[0] 100
- A. Clear Box Generator 102
- Clear Box Generator Options 103
- Clear Box Parameters 104
- inputs are 108
- OUTPUT_DQ 114
- Additional Information 116
- Typographic Conventions 117
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