Altera Stratix GX Guide de l'utilisateur télécharger pdf (Page 61)

Altera Corporation 3–15

January 2005 Stratix GX Transceiver User Guide

Basic Mode

Figure 3–13. Receiver Byte Deserialzer Data Recovery in Logic Array

Receiver Phase Compensation FIFO Buffer

The receiver phase compensation FIFO buffer is located at the FPGA logic

array interface in the receiver block and is four words deep. The buffer

compensates for the phase difference between the clock in the FPGA and

the operating clocks in the transceiver block.

In basic mode, the write port is clocked by the recovered clock from the

CRU. This clock is half the original rate if the byte deserializer is used. The

read clock is clocked by RX_CORECLK.

You can select RX_CORECLK as an optional receiver input port, and it can

also accept a clock supply. The clock that feeds the RX_CORECLK must be

derived from the RX_CLKOUT of its associated receiver channel. The

receiver phase compensation FIFO buffer can only account for phase

differences.

Gigabit Transceiver Block Logic Array

rx_out[19..10]

rx_out[9..0]

Byte Boundary

Selection Logic

rx_out_post[9..0]

rx_out_post[19..10]

{rx_out[9..0], rx_out_post[19..10]}

rx_out_post[19..0]

rx_out_align[19..0]

Phase

Compensation

FIFO

Buffer

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 317 318

Pas de commentaire

Altera Stratix GX Guide de l'utilisateur Page 61