Altera MAX 10 JTAG Manuel d'utilisateur

MAX 10 JTAG Boundary-Scan TestingUser GuideSubscribeSend FeedbackUG-M10JTAG2015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.com

Instruction Name InstructionBinaryDescriptionHIGHZ (1)00 0000 1011• Places the 1-bit bypass register between the TDI and TDO pins. The1-bit bypass reg

I/O Voltage Support in the JTAG Chain42015.05.04UG-M10JTAGSubscribeSend FeedbackA JTAG chain can contain several Altera and non-Altera devices.The TDO

Enabling and Disabling JTAG BST Circuitry52015.05.04UG-M10JTAGSubscribeSend FeedbackThe JTAG BST circuitry in MAX 10 devices is automatically enabled

Guidelines for JTAG BST62015.05.04UG-M10JTAGSubscribeSend FeedbackConsider the following guidelines when you perform BST with the device:• If the “10.

Boundary-Scan Description Language Support72015.05.04UG-M10JTAGSubscribeSend FeedbackThe BSDL—a subset of VHDL—provides a syntax that allows you to de

Additional Information for MAX 10 JTAGBoundary-Scan Testing User GuideA2015.05.04UG-M10JTAGSubscribeSend FeedbackDocument Revision History for MAX 10

ContentsOverview... 1-1JTAG BST Architectur

Overview12015.05.04UG-M10JTAGSubscribeSend FeedbackMAX® 10 devices support the IEEE Std.1149.1 (JTAG) boundary-scan testing (BST).When you perform BST

JTAG BST Architecture22015.05.04UG-M10JTAGSubscribeSend FeedbackMAX 10 JTAG interface uses four pins, TDI, TDO, TMS, and TCK.JTAG PinsTable 2-1: JTAG

Figure 2-1: JTAG Circuitry Functional Model• Test access port (TAP) controller—controls the JTAG BST.• TMS and TCK pins—operate the TAP controller.• T

Boundary-Scan Cells in MAX 10 I/O PinThe MAX 10 3-bit BSC contains the following registers:• Capture registers—connect to internal device data through

Table 2-2: BSC Capture and Update Register for MAX 10 DevicesPin TypeCaptures DrivesOutputCaptureRegisterOE CaptureRegisterInputCaptureRegisterOutputU

JTAG BST Operation Control32015.05.04UG-M10JTAGSubscribeSend FeedbackJTAG IDCODEThe IDCODE is unique for each MAX 10 device. Use this code to identify

JTAG Secure ModeIn JTAG secure mode, the device only allow SAMPLE/PRELOAD, BYPASS, EXTEST, and IDCODE JTAGinstructions.Related InformationMAX 10 FPGA