Altera Virtual JTAG IP Core Manuel d'utilisateur Page 25
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else
tdo <= bypass_reg;
endmodule
The decode logic is produced by defining a wire load to be active high whenever the IR of the Virtual JTAG
megafunction is 01. The IR scan shift is used to load the data into the IR of the Virtual JTAG megafunction.
The ir_in output port reflects the IR contents.
The Data Register logic contains a 4-bit shift register named tmp_reg. The always blocks shown for the
Data Register logic also contain the decode logic consisting of the load and sdr signals. The sdr signal is
the output of the Virtual JTAG megafunction that is asserted high during a DR scan shift operation. The
time during which the sdr output is asserted high is the time in which the data on tdi is valid. During that
time period, the data is shifted into the tmp_reg shift register. Therefore, tmp_reg gets the data from the
Virtual JTAG megafunction on the tdi output port during a DR scan operation.
There is a 1-bit register named bypass_reg whose output is connected with tdo logic to maintain the
continuity of the scan chain during idle or IR scan shift operation of the Virtual JTAG megafunction. The
tdo logic consists of outputs coming from tmp_reg and bypass_reg and connecting to the tdo input of the
Virtual JTAG megafunction. The tdo logic passes the data from tmp_reg to the Virtual JTAG megafunction
during DR scan shift operations.
The always block of a 4-bit counter also consists of some decode logic. This decode logic uses the load
signal and e1dr output signal of the Virtual JTAG megafunction to load the counter with the contents of
tmp_reg. The Virtual JTAG output signal e1dr is asserted high during a DR scan shift operation when all
the data is completely shifted into the tmp_reg and sdr has been de-asserted. In addition to sdr and e1dr,
there are other outputs from the Virtual JTAG megafunction that are asserted high to show various states
of the TAP controller and internal states of the Virtual JTAG megafunction. All of these signals can be used
to perform different logic operations as needed in your design.
Simulation Support
Virtual JTAG interface operations can be simulated using all Altera-supported simulators. The simulation
support is for DR and IR scan shift operations. For simulation purposes, a behavioral simulation model of
the megafunction is provided in both VHDL and Verilog HDL in the altera_mf libraries. The I/O structure
of the model is the same as the megafunction.
In its implementation, the Virtual JTAG megafunction connects to your design on one side and to the JTAG
port through the JTAG hub on the other side. However, a simulation model connects only to your design.
There is no simulation model for the JTAG circuit. Therefore, no stimuli can be provided from the JTAG
ports of the device to imitate the scan shift operations of the Virtual JTAG megafunction in simulation.
The scan operations in simulation are realized using the simulation model. The simulation model consists
of a signal generator, a model of the SLD hub, and the Virtual JTAG model. The stimuli defined in the wizard
are passed as parameters to this simulation model from the variation file. The simulation parameters are
listed in the table below. The signal generator then produces the necessary signals for Virtual JTAG
megafunction outputs such as tck, tdi, tms, and so forth.
The model is parameterized to allow the simulation of an unlimited number of Virtual JTAG instances. The
parameter sld_sim_action defines the strings used for IR and DR scan shifts. Each Virtual JTAG’s variation
file passes these parameters to the Virtual JTAG component. The Virtual JTAG’s variation file can always
Altera Corporation
Virtual JTAG Megafunction (sld_virtual_jtag)
Send Feedback
25
Simulation Support
UG-SLDVRTL
2014.03.19
- Introduction 1
- Device Family Support 2
- On-Chip Debugging Tool Suite 2
- JTAG Protocol 4
- JTAG Circuitry Architecture 5
- SLD Hub Finite State Machine 8
- Input Ports 10
- Output Ports 11
- UG-SLDVRTL 12
- 2014.03.19 12
- Parameters 13
- Simulation Model 15
- DescriptionArgumentsCommand 16
- DescriptionSetting 18
- Virtual IR Shift 20
- Virtual DR Shift 20
- Related Information 21
- Simulation Support 25
- CommentsParameter 26
- Altera Corporation 27
- Send Feedback 27
- Compiling the Design 28
- Third-Party Synthesis Support 29
- Binary PatternInstruction 30
- HUB IP Configuration Register 31
- SLD_NODE Info Register 31
- FunctionField 32
- AHDL Function Prototype 33
- VHDL Component Declaration 34
- VHDL LIBRARY-USE Declaration 35
- Write Logic 37
- Read Logic 38
- Runtime Communication 39
- Figure 20: Runtime Execution 40
- Document Revision History 42
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