Altera Transceiver Signal Integrity Development Kit, Stra Manuel d'utilisateur Page 56
- Page / 58
- Table des matières
- MARQUE LIVRES
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- MNL-01064-1.1 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- 1–2 Chapter 1: Overview 6
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 14
- Featured Device: Stratix V GX 15
- MAX II CPLD System Controller 17
- Configuration 22
- Installed 1 User image 23
- JTAG Header 25
- Status Elements 26
- Status LEDs 26
- Setup Elements 27
- Program Select Jumper 28
- Reset Push Button 28
- CPU Reset Push Button 28
- Clock Circuitry 29
- General-Purpose Clocks 30
- Embedded USB-Blaster Clocks 31
- Transceiver Channels 32
- SMA Connectors 33
- Backplane Connectors 34
- User-Defined Push Buttons 37
- User-Defined DIP Switch 38
- User-Defined LEDs 38
- Character LCD 39
- General User Input/Output 40
- 10/100/1000 Ethernet 41
- Components and Interfaces 42
- Transceiver Interfaces 43
- XFP Interface 43
- SFP+ Interface 44
- Flash Memory 45
- Power Supply 47
- Power Measurement 48
- Power Distribution System 50
- Temperature Sense 50
- Notes to Table 2–46: 51
- A. Board Revision History 53
- Typographic Conventions 58
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