Altera Transceiver Signal Integrity Development Kit, Stra Manuel d'utilisateur télécharger pdf (Page 5)

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

1. Overview

This document describes the hardware features of the Stratix

V GX transceiver signal

integrity development board, including the detailed pin-out and component reference

information required to create custom FPGA designs that interface with all

components of the board.

General Description

The Transceiver Signal Integrity Development Kit, Stratix V GX Edition, allows you to

evaluate the performance the Stratix V GX FPGA which is optimized for

high-performance and high-bandwidth applications with integrated transceivers

supporting backplane, chip-to-chip, and chip-to-module operation.

f For more information on the following topics, refer to the respective documents:

■ Setting up the development board and using the included software, refer to the

Transceiver Signal Integrity Development Kit, Stratix V GX Edition User Guide.

■ Stratix V device family, refer to the Stratix V Device Handbook.

Board Component Blocks

The Stratix V GX transceiver signal integrity development board provides a hardware

platform for evaluating the performance and signal integrity features of the Altera

Stratix V GX device. The development board features the following major component

blocks:

■ Altera Stratix V GX FPGA (5SGXEA7N2F40C2N) in a 1517-pin FineLine BGA

Package (migratable to Stratix V GT FPGA 5SGTMC7K3F40C2)

■ 622,000 LEs

■ 358,500 adaptive logic modules (ALMs)

■ 50-Mbits embedded memory

■ 512 18x18-bit multipliers

■ 32 transceivers (12.5 Gbps)

■ 174 LVDS transmit channels

■ 28 phase locked loops (PLLs)

■ 696 user I/Os

■ 850-mV core voltage

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Altera Transceiver Signal Integrity Development Kit, Stra Manuel d'utilisateur Page 5