Altera Stratix V GX FPGA Development Board Manuel d'utilisateur Page 71
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- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 13
- MAX V CPLD System Controller 14
- Configuration 20
- Figure 2–3. JTAG Chain 22
- Note to Table 2–9: 24
- Figure 2–4. PFL Configuration 25
- Status LEDs 26
- Board Settings DIP Switch 27
- JTAG Control DIP Switch 28
- MAX V Reset Push Button 29
- Program Load Push Button 29
- Program Select Push Button 30
- CPU Reset Push Button 30
- Clock Circuitry 31
- Off-Board Clock Input/Output 33
- General User Input/Output 34
- User-Defined DIP Switches 35
- General User-Defined LEDs 36
- HSMC User-Defined LEDs 37
- Components and Interfaces 39
- CROSS MAX 40
- CROSS MIN 40
- 10/100/1000 Ethernet 42
- SDI Video Output/Input 51
- 40G QSFP Connector 53
- RLDRAM II 61
- Power Supply 65
- Power Measurement 67
- Temperature Sense 68
- Notes to Table 2–63: 69
- A. Board Revision History 71
- Document Revision History 74
- Note to Table: 75
- Typographic Conventions 76
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