
2–54 Chapter 2: Board Components
Memory
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Table 2–50 lists the QDRII+ top port 0 pin assignments, signal names, and functions.
The signal names and types are relative to the Stratix IV GX device in terms of I/O
setting and direction.
Table 2–50. QDRII+ Top Port 0 Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board Reference Description
Schematic Signal Name
I/O Standard
Stratix IV GX
Device
Pin Number
U22.A10 Address bus
QDR2TOP0_A19
1.5-V HSTL Class I
A28
U22.A3 Address bus
QDR2TOP0_A18
J24
U22.A9 Address bus
QDR2TOP0_A17
C28
U22.R7 Address bus
QDR2TOP0_A16
G28
U22.R5 Address bus
QDR2TOP0_A15
C30
U22.R4 Address bus
QDR2TOP0_A14
C29
U22.R3 Address bus
QDR2TOP0_A13
B28
U22.P8 Address bus
QDR2TOP0_A12
R24
U22.P7 Address bus
QDR2TOP0_A11
N20
U22.P5 Address bus
QDR2TOP0_A10
A31
U22.P4 Address bus
QDR2TOP0_A9
A29
U22.N7 Address bus
QDR2TOP0_A8
P20
U22.N6 Address bus
QDR2TOP0_A7
B31
U22.N5 Address bus
QDR2TOP0_A6
B29
U22.C7 Address bus
QDR2TOP0_A5
D27
U22.C5 Address bus
QDR2TOP0_A4
F26
U22.B8 Address bus
QDR2TOP0_A3
A27
U22.B4 Address bus
QDR2TOP0_A2
G26
U22.R8 Address bus
QDR2TOP0_A1
P24
U22.R9 Address bus
QDR2TOP0_A0
N21
U22.N2 Write data bus
QDR2TOP0_D17
B25
U22.M3 Write data bus
QDR2TOP0_D16
G24
U22.L3 Write data bus
QDR2TOP0_D15
F24
U22.J3 Write data bus
QDR2TOP0_D14
M24
U22.G2 Write data bus
QDR2TOP0_D13
K23
U22.F3 Write data bus
QDR2TOP0_D12
M23
U22.D2 Write data bus
QDR2TOP0_D11
R22
U22.C3 Write data bus
QDR2TOP0_D10
N22
U22.B3 Write data bus
QDR2TOP0_D9
P22
U22.C11 Write data bus
QDR2TOP0_D8
A26
U22.D11 Write data bus
QDR2TOP0_D7
B26
U22.E10 Write data bus
QDR2TOP0_D6
C25
U22.G11 Write data bus
QDR2TOP0_D5
C26
U22.J11 Write data bus
QDR2TOP0_D4
D25
U22.K10 Write data bus
QDR2TOP0_D3
D26
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