Altera Stratix IV GX FPGA Development Board Manuel d'utilisateur télécharger pdf (Page 48)

2–40 Chapter 2: Board Components

Components and Interfaces

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

J2.16 Transceiver RX bit 4n

HSMB_RX_N4

1.4-V PCML

J2.17 Transceiver TX bit 3

HSMB_TX_P3

B36

J2.18 Transceiver RX bit 3

HSMB_RX_P3

C38

J2.19 Transceiver TX bit 3n

HSMB_TX_N3

B37

J2.20 Transceiver RX bit 3n

HSMB_RX_N3

C39

J2.21 Transceiver TX bit 2

HSMB_TX_P2

D36

J2.22 Transceiver RX bit 2

HSMB_RX_P2

E38

J2.23 Transceiver TX bit 2n

HSMB_TX_N2

D37

J2.24 Transceiver RX bit 2n

HSMB_RX_N2

E39

J2.25 Transceiver TX bit 1

HSMB_TX_P1

K36

J2.26 Transceiver RX bit 1

HSMB_RX_P1

L38

J2.27 Transceiver TX bit 1n

HSMB_TX_N1

K37

J2.28 Transceiver RX bit 1n

HSMB_RX_N1

L39

J2.29 Transceiver TX bit 0

HSMB_TX_P0

M36

J2.30 Transceiver RX bit 0

HSMB_RX_P0

N38

J2.31 Transceiver TX bit 0n

HSMB_TX_N0

M37

J2.32 Transceiver RX bit 0n

HSMB_RX_N0

N39

J2.33 Management serial data

HSMB_SDA

2.5-V

AF29

J2.34 Management serial clock

HSMB_SCL

AB27

J2.35 JTAG clock signal

FPGA_JTAG_TCK

—

J2.36 JTAG mode select signal

FPGA_JTAG_TMS

—

J2.37 JTAG data output

HSMB_JTAG_TDO

—

J2.38 JTAG data input

HSMB_JTAG_TDI

—

J2.39 Dedicated CMOS clock out

HSMB_CLK_OUT0

AK29

J2.40 Dedicated CMOS clock in

HSMB_CLK_IN0

AA35

J2.41 Dedicated CMOS I/O bit 0

HSMB_D0

AP10

J2.42 Dedicated CMOS I/O bit 1

HSMB_D1

AN10

J2.43 Dedicated CMOS I/O bit 2

HSMB_D2

AW8

J2.44 Dedicated CMOS I/O bit 3

HSMB_D3

AV8

J2.47 LVDS TX bit 0 or CMOS bit 4

HSMB_TX_D_P0

LVDS or 2.5-V

W12

J2.48 LVDS RX bit 0 or CMOS bit 5

HSMB_RX_D_P0

J2.49 LVDS TX bit 0n or CMOS bit 6

HSMB_TX_D_N0

W11

J2.50 LVDS RX bit 0n or CMOS bit 7

HSMB_RX_D_N0

J2.53 LVDS TX bit 1 or CMOS bit 8

HSMB_TX_D_P1

V12

J2.54 LVDS RX bit 1 or CMOS bit 9

HSMB_RX_D_P1

J2.55 LVDS TX bit 1n or CMOS bit 10

HSMB_TX_D_N1

V11

J2.56 LVDS RX bit 1n or CMOS bit 11

HSMB_RX_D_N1

J2.59 LVDS TX bit 2 or CMOS bit 12

HSMB_TX_D_P2

V10

Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Description Schematic Signal

Name

I/O Standard

Stratix IV GX

Device

Pin Number

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 77 78

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Altera Stratix IV GX FPGA Development Board Manuel d'utilisateur Page 48

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