Altera RLDRAM II Controller MegaCore Function Manuel d'utilisateur Page 31
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- Table des matières
- MARQUE LIVRES
- RLDRAM II Controller 1
- MegaCore Function User Guide 1
- UG-RLDRAM-8.1 2
- Contents 3
- Additional Information 4
- 1. About This MegaCore 5
- Function 5
- Features 6
- General 6
- Description 6
- (1) Non-DQS mode only 7
- Performance 8
- Utilization 8
- 2. Functional Description 11
- Control Logic 12
- Datapath 13
- <signal>_1 are present 14
- Memory Clock Generator 15
- Pipeline Registers 16
- DQS Group 16
- Functional Description 17
- Notes to Figure 2–4: 17
- Datapath Example 18
- Figure 2–6. Example Datapath 19
- Device-Level 22
- Configuration 22
- Example Design 24
- Interfaces 26
- Refreshes 31
- system signals 32
- Direction Description 33
- Parameters 38
- Parameter Range Description 40
- Project Settings 42
- MegaCore 43
- Verification 43
- MegaCore Verification 44
- 3. Getting Started 45
- RLDRAM II 46
- Controller 46
- Walkthrough 46
- Launch IP Toolbench 48
- Step 1: Parameterize 49
- Step 2: Constraints 51
- Step 3: Set Up Simulation 52
- Step 4: Generate 52
- Simulate the 55
- Simulate the Example Design 56
- Edit the PLL 57
- Compile the 58
- Program a 59
- Implement Your 59
- Set Up Licensing 59
- Typographic 62
- Conventions 62
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