Altera Reed-Solomon II MegaCore Function Manuel d'utilisateur Page 3

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About the Reed-Solomon II IP Core
1
2015.05.01
UG-01090
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Altera DSP IP Core Features
Avalon
®
Streaming (Avalon-ST) interfaces
DSP Builder ready
Testbenches to verify the IP core
IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Reed-Solomon II IP Core Features
High-performance encoder or decoder for error detection and correction:
Fully parameterizable:
Number of channels
Number of bits per symbol
Number of symbols per codeword
Number of check symbols per codeword
Field polynomial
Erasures-supporting decoder—-the decoder can correct symbol errors up to the number of check
symbols, if you give the location of the errors to the decoder
Error symbol output—the decoder provides the error values
Bit error output—either split count or full count
Multiple channels for resource sharing
DSP IP Core Device Family Support
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