Altera QDRII SRAM Controller MegaCore Function Manuel d'utilisateur télécharger pdf (Page 53)

Altera Corporation MegaCore Version 9.1 3–21

November 2009 QDRII SRAM Controller MegaCore Function User Guide

Functional Description

Figure 3–18. Simultaneous Read & Write—Burst of Two

Burst of Four (Wide Mode)

For the burst of four (wide mode) all the data is present in one clock cycle.

Similarly to the two cycles, you must alternate the read and write

commands on the QDRII SRAM interface. As a result, there is a pause

when both the read and write commands arrive simultaneously on the

Avalon interfaces. The first read is buffered and then the consecutive read

is delayed by one clock cycle, refer to Figure 3–19 on page 3–22.

51 52 52

0102 0304 0304

01 02 02

1112 1314 1314

51 01 52 02 02

11 12 13 14 14

01 02 03 04 04

avl_clk

avl_read

avl_adr_rd[19:0]

avl_wait_request_rd

avl_data_read_valid

avl_data_rd[17:0]

avl_write

avl_adr_wr[19:0]

avl_wait_request_wr

avl_data_wr[17:0]

qdrii_k

qdrii_a[19:0]

qdrii_d[17:0]

qdrii_wpsn

qdrii_rpsn

qdrii_cqn

qdrii_cq

qdrii_q[17:0]

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 67 68

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Altera QDRII SRAM Controller MegaCore Function Manuel d'utilisateur Page 53