Altera Nios Development Board Cyclone II Edition Manuel d'utilisateur télécharger pdf (Page 26)

2–14 Reference Manual Altera Corporation

Nios Development Board Cyclone II Edition May 2007

Board Components

C25 94 Byte Enable 0 enet_be_n0

C24 95 Byte Enable 1 enet_be_n1

D26 96 Byte Enable 2 enet_be_n2

D25 97 Byte Enable 3 enet_be_n3

E20 31 Read enet_ior_n

D16 32 Write enet_iow_n

H8 78 Address Line fe_a1

D11 79 Address Line fe_a2

E8 80 Address Line fe_a3

B14 81 Address Line fe_a4

A14 82 Address Line fe_a5

F14 83 Address Line fe_a6

G14 84 Address Line fe_a7

F13 85 Address Line fe_a8

G13 86 Address Line fe_a9

C15 87 Address Line fe_a10

B15 88 Address Line fe_a11

B16 89 Address Line fe_a12

C16 90 Address Line fe_a13

D15 91 Address Line fe_a14

E15 92 Address Line fe_a15

D8 107 Data Line fe_d0

C8 106 Data Line fe_d1

F10 105 Data Line fe_d2

G10 104 Data Line fe_d3

D9 102 Data Line fe_d4

C9 101 Data Line fe_d5

B8 100 Data Line fe_d6

A8 99 Data Line fe_d7

H11 76 Data Line fe_d8

H12 75 Data Line fe_d9

F11 74 Data Line fe_d10

E10 73 Data Line fe_d11

B9 71 Data Line fe_d12

Table 2–9. Ethernet MAC/PHY Pin Table (Continued)

FPGA Pin U4 Pin Pin Function Board Net Name (1)

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 63 64

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Altera Nios Development Board Cyclone II Edition Manuel d'utilisateur Page 26