Altera MAX V CPLD Manuel d'utilisateur télécharger pdf (Page 27)

Chapter 5: Board Test System 5–13

Using the Board Test System

January 2011 Altera Corporation MAX V CPLD Development Kit User Guide

The SPI EEPROM Tab

This tab (Figure 5–10) allows you to read and write 1-K data to a user self-mounted

SPI EEPROM located at U6 on the development board.

1 EEPROMs are not included with the MAX V CPLD Development Kit. This test is

designed for a Microchip Technology EEPROM in the TSSOP-8 package. For more

information on the recommended EEPROMS, refer to the MAX V CPLD Development

Board Reference Manual.

The following sections describe the controls on the SPI EEPROM tab.

Address Display

Displays addresses of the SPI EEPROM.

Write

Writes all of the current 1-Kb data to the SPI EEPROM.

Figure 5–10. The SPI EEPROM Tab

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Altera MAX V CPLD Manuel d'utilisateur Page 27